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ORCIDCarlos Beltrán Almeida
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2000 – 2009
- 2008
[j3]José A. Soares Augusto
, Carlos Beltrán Almeida:
A Tool for Single-Fault Diagnosis in Linear Analog Circuits with Tolerance Using the T-Vector Approach. VLSI Design 2008: 630951:1-630951:8 (2008)- 2003
- [c5]J. Soares Augusto, Carlos Beltrán Almeida, H. C. Campos Neto:
A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits. FPL 2003: 818-827 - 2001
- [j2]Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva:
A System Level Boundary Scan Controller Board for VME Applications. J. Electron. Test. 17(3-4): 299-310 (2001) - 2000
- [c4]José A. Soares Augusto, Carlos F. Beltrán Almeida:
Analog fault diagnosis in nonlinear DC circuits with an evolutionary algorithm. CEC 2000: 609-616 - [c3]Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva:
A system level boundary scan controller board for VME applications [to CERN experiments]. ETW 2000: 153-158
1990 – 1999
- 1997
- [c2]Anton V. Chichkov, Carlos Beltrán Almeida:
A hardware/software partitioning algorithm for custom computing machines. FPL 1997: 274-283 - 1991
- [j1]João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves:
A methodology for testability enhancement at layout level. J. Electron. Test. 1(4): 287-299 (1991) - 1990
- [c1]João Paulo Teixeira, Isabel C. Teixeira, Carlos F. Beltrán Almeida, Fernando M. Gonçalves, Júlio Gonçalves, R. Crespo:
A strategy for testability enhancement at layout level. EURO-DAC 1990: 413-417
Coauthor Index
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