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2020 – today
- 2024
[c22]Luc Romain, Paul-Patrick Nordmann, Benoit Nadeau-Dostie, Lori Schramm, Martin Keim:
Combining Built-In Redundancy Analysis with ECC for Memory Testing. ETS 2024: 1-6- 2023
- [c21]Cyrille Dray, Khushal Gelda, Benoit Nadeau-Dostie, Wei Zou, Luc Romain, Jongsin Yun, Harshitha Kodali, Lori Schramm, Martin Keim:
Transitioning eMRAM from Pilot Project to Volume Production. ITC 2023: 82-86 - 2022
- [c20]Wei Zou, Benoit Nadeau-Dostie:
Configurable BISR Chain For Fast Repair Data Loading. ITC 2022: 56-62 - 2020
- [c19]Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Cyrille Dray, El Mehdi Boujamaa:
MBIST Support for Reliable eMRAM Sensing. ETS 2020: 1-6 - [c18]Benoit Nadeau-Dostie, Luc Romain:
Memory repair logic sharing techniques and their impact on yield. ITC 2020: 1-5 - [c17]Jongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Lori Schramm, Cyrille Dray, El Mehdi Boujamaa, Khushal Gelda:
MBIST Supported Multi Step Trim for Reliable eMRAM Sensing. ITC 2020: 1-5
2010 – 2019
- 2018
- [c16]Venkat Yellapragada, Suresh Raman, Banadappa Shivaray, Luc Romain, Benoit Nadeau-Dostie, Martin Keim, Jean-Francois Cote, Albert Au, Giri Podichetty, Ashok Anbalan:
Implementing Design-for-Test Within a Tile-Based Design Methodology - Challenges and Solutions. ITC-Asia 2018: 43-48 - 2017
- [c15]Jais Abraham, Uttam Garg, Glenn Colón-Bonet, Ramesh Sharma, Chennian Di, Benoit Nadeau-Dostie, Etienne Racine, Martin Keim:
Adapting an industrial memory BIST solution for testing CAMs. ITC-Asia 2017: 112-117 - 2015
- [j8]Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer:
Low-Power Programmable PRPG With Test Compression Capabilities. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1063-1076 (2015) - 2014
- [p1]Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin:
Timing-Aware ATPG. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 49-72 - 2012
- [j7]Joon-Sung Yang, Nur A. Touba, Benoit Nadeau-Dostie:
Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops. IEEE Trans. Computers 61(10): 1473-1483 (2012) - [c14]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie:
Test generator with preselected toggling for low power built-in self-test. VTS 2012: 1-6 - 2011
- [c13]Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer:
Power Aware Embedded Test. Asian Test Symposium 2011: 511-516
2000 – 2009
- 2009
- [j6]Benoit Nadeau-Dostie, Saman Adham, Russell Abbott:
Improved Core Isolation and Access for Hierarchical Embedded Test. IEEE Des. Test Comput. 26(1): 18-25 (2009) - [c12]Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba:
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points. DFT 2009: 20-28 - [c11]Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba:
Test point insertion using functional flip-flops to drive control points. ITC 2009: 1-10 - 2008
- [c10]Benoit Nadeau-Dostie, Kiyoshi Takeshita, Jean-Francois Cote:
Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks. ITC 2008: 1-10 - 2006
- [c9]Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie:
OCI: Open Compression Interface. ITC 2006: 1-4 - 2004
- [c8]Saman Adham, Benoit Nadeau-Dostie:
A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs. MTDT 2004: 98-101 - 2002
- [c7]Stephen K. Sunter, Benoit Nadeau-Dostie:
Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost. ITC 2002: 446-455
1990 – 1999
- 1999
- [j5]Samir Boubezari, Eduard Cerny, Bozena Kaminska, Benoit Nadeau-Dostie:
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(9): 1327-1340 (1999) - [c6]Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras:
An embedded technique for at-speed interconnect testing. ITC 1999: 431-438 - 1996
- [j4]Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie:
Built-In Self-Test: Assuring System Integrity. Computer 29(11): 39-45 (1996) - 1995
- [c5]Benoit Nadeau-Dostie, Harry Hulvershorn, Saman Adham:
A New Hardware Fault Insertion Scheme for System Diagnostics Verification. ITC 1995: 994-1002 - 1994
- [j3]Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan:
ScanBist: A Multifrequency Scan-Based BIST Method. IEEE Des. Test Comput. 11(1): 7-17 (1994) - 1992
- [j2]Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski:
BIST of PCB interconnects using boundary-scan architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10): 1278-1288 (1992) - [c4]Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan:
ScanBIST: A Multi-frequency Scan-based BIST Method. ITC 1992: 506-513 - [c3]Michael M. Y. Hui, Benoit Nadeau-Dostie:
Scan testing of latch arrays. VTS 1992: 31-36 - 1990
- [j1]Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal:
Serial Interfacing for Embedded-Memory Testing. IEEE Des. Test Comput. 7(2): 52-63 (1990) - [c2]Fidel Muradali, Vinod K. Agarwal, Benoit Nadeau-Dostie:
A new procedure for weighted random built-in self-test. ITC 1990: 660-669
1980 – 1989
- 1989
- [c1]Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie:
Testing of Glue Logic Interconnects Using Boundary Scan Architecture. ITC 1989: 700-711
Coauthor Index
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