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2000 – 2009
- 2004
[c8]Stephen Pateras:
Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both. ITC 2004: 1413- 2003
- [j3]Stephen Pateras:
Achieving At-Speed Structural Test. IEEE Des. Test Comput. 20(5): 26-33 (2003) - 2002
- [j2]Stephen Pateras:
IP for Embedded Diagnosis. IEEE Des. Test Comput. 19(3): 46-55 (2002) - [c7]Stephen Pateras:
Embedded Diagnosis IP. DATE 2002: 242-243 - 2000
- [c6]Martin Bell, Givargis Danialy, Michael C. Howells, Stephen Pateras:
Bridging the gap between embedded test and ATE. ITC 2000: 55-63
1990 – 1999
- 1999
- [c5]Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras:
An embedded technique for at-speed interconnect testing. ITC 1999: 431-438 - 1997
- [j1]William V. Huott, Timothy J. Koprowski, Bryan J. Robbins, Mary P. Kusko, Stephen Pateras, Dale E. Hoffman, Timothy G. McNamara, Thomas J. Snethen:
Advanced microprocessor test strategy and methodology. IBM J. Res. Dev. 41(4&5): 611-628 (1997) - 1995
- [c4]Stephen Pateras, Martin S. Schmookler:
Avoiding Unknown States When Scanning Mutually Exclusive Latches. ITC 1995: 311-318 - 1991
- [c3]Stephen Pateras, Janusz Rajski:
Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. DAC 1991: 347-352 - [c2]Stephen Pateras, Janusz Rajski:
Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. ITC 1991: 473-482
1980 – 1989
- 1988
- [c1]Stephen Pateras, Janusz Rajski:
A self-reconfiguration scheme for fault-tolerant VLSI processor arrays. ICCD 1988: 560-563
Coauthor Index
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