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ORCIDBen Bennetts
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2000 – 2009
- 2007
[c8]Ben Bennetts:
Electronics Design-for-Test: Past, Present and Future. ETS 2007: 4- 2006
- [c7]Bill Eklow, Ben Bennetts:
New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG). ETS 2006: 253-254 - [c6]Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, Jean-Francois Cote:
IEEE P1687: Toward Standardized Access of Embedded Instrumentation. ITC 2006: 1-8 - 2005
- [c5]Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts:
IJTAG (internal JTAG): a step toward a DFT standard. ITC 2005: 8 - 2004
- [c4]Stephen K. Sunter, Adam Osseiran, Adam Cron, Neil G. Jacobson, Dave Bonnett, Bill Eklow, Carl Barnhart, Ben Bennetts:
Status of IEEE Testability Standards 1149.4, 1532 and 1149.6. DATE 2004: 1184-1191 - 2003
- [j16]Monica Lobetti Bodoni, Ben Bennetts:
Guest Editors' Introduction: Board Test. IEEE Des. Test Comput. 20(2): 5-7 (2003) - [j15]Erik Jan Marinissen
, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts:
Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. IEEE Des. Test Comput. 20(2): 8-18 (2003)
1990 – 1999
- 1999
- [j14]Tony Ambler, Ben Bennetts:
Guest Editors' Introduction: Test and the Product Life Cycle. IEEE Des. Test Comput. 16(3): 20-22 (1999) - [j13]Mike Wondolowski, Ben Bennetts, Adam W. Ley:
Boundary Scan: The Internet of Test. IEEE Des. Test Comput. 16(3): 34-43 (1999) - 1996
- [j12]Bernd Könemann, Ben Bennetts, Najmi T. Jarwala, Benoit Nadeau-Dostie:
Built-In Self-Test: Assuring System Integrity. Computer 29(11): 39-45 (1996) - 1995
- [j11]Ben Bennetts:
Guest Editor's Introduction. IEEE Des. Test Comput. 12(2): 6-7 (1995) - 1993
- [j10]Ben Bennetts:
Essential reading for the basics and implementation of boundary scan: Parker, K PThe boundary-scan handbook Kluwer Academic, Dordrecht, The Netherlands (1992) ISBN 0 7923 9270 1, £48.00/Dfl. 160.00, pp 282. Microprocess. Microsystems 17(5): 304 (1993) - 1992
- [c3]Ben Bennetts:
Progress in DFT: A Personal View. ITC 1992: 19-20 - [c2]Frank Bouwman, Steven Oostdijk, Rudi Stans, Ben Bennetts, Frans P. M. Beenker:
Macro Testability: The Results of Production Device Applications. ITC 1992: 232-241 - 1991
- [j9]R. G. Bennetts, A. Osseyran:
IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status. J. Electron. Test. 2(1): 11-25 (1991) - [c1]R. G. Bennetts:
Scan Technology at Work. Fault-Tolerant Computing Systems 1991: 124-135 - 1990
- [j8]Ben Bennetts:
Test Technology in Europe. IEEE Des. Test Comput. 7(1): 6-8 (1990)
1980 – 1989
- 1986
- [j7]R. G. Bennetts:
Digital test text caters for academia and researchers: Hideo Fujiwara 'Logic testing and design for testability' MIT Press, Cambridge, MA, USA (1985) £34.95 pp x + 284. Microprocess. Microsystems 10(3): 173 (1986)
1970 – 1979
- 1979
- [j6]R. G. Bennetts:
Fault tolerance and digital systems. Microprocess. Microsystems 3(8): 365-373 (1979) - 1976
- [j5]R. G. Bennetts, Roy V. Scott:
Recent Developments in the Theory and Practice of Testable Logic Design. Computer 9(6): 47-63 (1976) - 1972
- [j4]R. G. Bennetts:
A realistic approach to detection test generation for combinatorial logic circuits. Comput. J. 15(3): 238-246 (1972) - 1971
- [j3]Ben Bennetts, D. W. Lewin:
Fault Diagnosis of Digital Systems - A Review. Comput. J. 14(2): 199-206 (1971) - [j2]R. G. Bennetts, D. W. Lewin:
Fault Diagnosis of Digital Systems - a Review. Computer 4(4): 12-20 (1971) - [j1]R. G. Bennetts:
An Improved Method of Prime C-Class Derivation in the State Reduction of Sequential Networks. IEEE Trans. Computers 20(2): 229-231 (1971)
Coauthor Index
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