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Journal Articles
- 2021
[j14]Alessandro Frigerio
, Bart Vermeulen, Kees G. W. Goossens:
Automotive Architecture Topologies: Analysis for Safety-Critical Autonomous Vehicle Applications. IEEE Access 9: 62837-62846 (2021)- 2011
- [j13]Bart Vermeulen, Kees Goossens:
Interactive Debug of SoCs with Multiple Clocks. IEEE Des. Test Comput. 28(3): 44-51 (2011) - 2010
- [j12]Bart Vermeulen, Peter Goos, Martina Vandebroek:
Obtaining more information from conjoint experiments by best-worst choices. Comput. Stat. Data Anal. 54(6): 1426-1433 (2010) - [j11]Willem W. Verstraeten, Bart Vermeulen, Jan Stuckens, Stefaan Lhermitte, Dimitry Van der Zande, Marc Van Ranst, Pol Coppin:
Webcams for Bird Detection and Monitoring: A Demonstration Study. Sensors 10(4): 3480-3503 (2010) - 2008
- [j10]Bart Vermeulen:
Functional Debug Techniques for Embedded Systems. IEEE Des. Test Comput. 25(3): 208-215 (2008) - [j9]Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick:
Overview of Debug Standardization Activities. IEEE Des. Test Comput. 25(3): 258-267 (2008) - [j8]Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Bart Vermeulen, Marc J. M. Heijligers:
Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis. IEEE J. Solid State Circuits 43(1): 192-201 (2008) - 2007
- [j7]Bart Vermeulen, Sjaak Bakker:
Debug architecture for the En-II system chip. IET Comput. Digit. Tech. 1(6): 678-684 (2007) - 2005
- [j6]Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen:
Optimal Interconnect ATPG Under a Ground-Bounce Constraint. J. Electron. Test. 21(1): 17-31 (2005) - 2003
- [j5]Bart Vermeulen, John Dielissen, Kees Goossens, Calin Ciordas:
Bringing communication networks on a chip: test and verification implications. IEEE Commun. Mag. 41(9): 74-81 (2003) - [j4]Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts:
Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. IEEE Des. Test Comput. 20(2): 8-18 (2003) - [j3]Sandeep Kumar Goel, Bart Vermeulen:
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. J. Electron. Test. 19(4): 407-416 (2003) - [j2]Bart Vermeulen, Tom Waayers, Sjaak Bakker:
Multi-TAP Controller Architecture for Digital System Chips. J. Electron. Test. 19(4): 417-424 (2003) - 2002
- [j1]Bart Vermeulen, Sandeep Kumar Goel:
Design for Debug: Catching Design Errors in Digital Chips. IEEE Des. Test Comput. 19(3): 37-45 (2002)
Conference and Workshop Papers
- 2021
- [c37]Alessandro Frigerio, Bart Vermeulen, Kees Goossens:
Isolation of redundant and mixed-critical automotive applications: effects on the system architecture. VTC Spring 2021: 1-6 - 2020
- [c36]Tjerk Bijlsma, Andrii Buriachevskyi, Alessandro Frigerio, Yuting Fu, Kees Goossens, Ali Osman Örs, Pieter J. van der Perk, Andrei Sergeevich Terechko, Bart Vermeulen:
A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles. DATE 2020: 1175-1180 - 2019
- [c35]Alessandro Frigerio, Bart Vermeulen, Kees Goossens:
Component-Level ASIL Decomposition for Automotive Architectures. DSN Workshops 2019: 62-69 - 2018
- [c34]Alessandro Frigerio, Bart Vermeulen, Kees Goossens:
A Generic Method for a Bottom-Up ASIL Decomposition. SAFECOMP 2018: 12-26 - 2016
- [c33]Abhijit K. Deb, Bart Vermeulen, Luc van Dijk:
Overview of Health Monitoring Techniques for Reliability. ERMAVSS@DATE 2016: 30-33 - 2014
- [c32]Alexander Kordes, Bart Vermeulen, Abhijit K. Deb, Michael G. Wahl:
Startup error detection and containment to improve the robustness of hybrid FlexRay networks. DATE 2014: 1-6 - [c31]Sujan Pandey, Bart Vermeulen:
Transient errors resiliency analysis technique for automotive safety critical applications. DATE 2014: 1-4 - 2012
- [c30]Arnaldo Azevedo, Bart Vermeulen, Kees Goossens:
Architecture and design flow for a debug event distribution interconnect. ICCD 2012: 439-444 - 2011
- [c29]Thijs Schenkelaars, Bart Vermeulen, Kees Goossens:
Optimal scheduling of switched FlexRay networks. DATE 2011: 926-931 - 2010
- [c28]Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen:
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism. DSD 2010: 531-537 - [c27]Paul Milbredt, Bart Vermeulen, Gökhan Tabanoglu, Martin Lukasiewycz:
Switched FlexRay: Increasing the effective bandwidth and safety of FlexRay networks. ETFA 2010: 1-8 - [c26]Erik Larsson, Bart Vermeulen, Kees Goossens:
A distributed architecture to check global properties for post-silicon debug. ETS 2010: 182-187 - [c25]Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen:
New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism. ETS 2010: 243 - [c24]Bart Vermeulen, Kees Goossens:
Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks. HLDVT 2010: 1-8 - [c23]Timon D. ter Braak, S. T. Burgess, H. Hurskainen, Hans G. Kerkhoff, Bart Vermeulen, Xiao Zhang:
On-line dependability enhancement of multiprocessor SoCs by resource management. SoC 2010: 103-110 - [c22]Andreas Eckel, Paul Milbredt, Zaid Al-Ars, Stefan Schneele, Bart Vermeulen, György Csertán, Christoph Scheerer, Neeraj Suri, Abdelmajid Khelil, Gerhard Fohler:
INDEXYS, a Logical Step beyond GENESYS. SAFECOMP 2010: 431-451 - 2009
- [c21]Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad:
A high-level debug environment for communication-centric debug. DATE 2009: 202-207 - 2008
- [c20]Miron Abramovici, Kees Goossens, Bart Vermeulen, Jack Greenbaum, Neal Stollon, Adam Donlin:
You can catch more bugs with transaction level honey. CODES+ISSS 2008: 121-124 - [c19]Jeroen Geuzebroek, Bart Vermeulen:
Integration of Hardware Assertions in Systems-on-Chip. ITC 2008: 1-10 - [c18]Bart Vermeulen, Kees Goossens, Siddharth Umrani:
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip. NOCS 2008: 3-12 - 2007
- [c17]Udaya Seshua, Nagaraju Bussa, Bart Vermeulen:
A Run-Time Memory Protection Methodology. ASP-DAC 2007: 498-503 - [c16]Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek:
Communication-Centric SoC Debug Using Transactions. ETS 2007: 69-76 - [c15]Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek:
Transaction-Based Communication-Centric Debug. NOCS 2007: 95-106 - 2005
- [c14]Kees van Kaam, Bart Vermeulen, Henk Jan Bergveld:
Test and debug features of the RTO7 chip. ITC 2005: 10 - 2004
- [c13]Bart Vermeulen, Mohammad Zalfany Urfianto, Sandeep Kumar Goel:
Automatic generation of breakpoint hardware for silicon debug. DAC 2004: 514-517 - [c12]Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge:
Trends in Testing Integrated Circuits. ITC 2004: 688-697 - 2003
- [c11]Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller:
Creating Value Through Test. DATE 2003: 10402-10409 - [c10]Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen:
Optimal Interconnect ATPG Under a Ground-Bounce Constraint. ITC 2003: 369-378 - 2002
- [c9]Sandeep Kumar Goel, Bart Vermeulen:
Data invalidation analysis for scan-based debug on multiple-clock system chips. ETW 2002: 61-66 - [c8]Bart Vermeulen, Tom Waayers, Sjaak Bakker:
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. ITC 2002: 55-63 - [c7]Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel:
Core-Based Scan Architecture for Silicon Debug. ITC 2002: 638-647 - [c6]Sandeep Kumar Goel, Bart Vermeulen:
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. ITC 2002: 1103-1110 - [c5]Bart Vermeulen:
TAPS All Over My Chips! So Now What Do I Do? ITC 2002: 1190 - [c4]Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark:
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? VTS 2002: 445-446 - 2001
- [c3]Bart Vermeulen, Steven Oostdijk, Frank Bouwman:
Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip. ITC 2001: 121-130 - 2000
- [c2]Bart Vermeulen, Gert-Jan van Rootselaar:
Silicon debug of a co-processor array for video applications. HLDVT 2000: 47-52 - 1999
- [c1]Gert-Jan van Rootselaar, Bart Vermeulen:
Silicon debug: scan chains alone are not enough. ITC 1999: 892-902
Coauthor Index
aka: Kees G. W. Goossens
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