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2010 – 2019
- 2013
[j7]Daniel Arumí
, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 301-312 (2013)- 2012
- [j6]Bram Kruseman, Bratislav Tasic, Camelia Hora, Jos Dohmen, Hamidreza Hashempour, Maikel van Beurden, Yizi Xing:
Defect Oriented Testing for Analog/Mixed-Signal Designs. IEEE Des. Test Comput. 29(5): 72-80 (2012) - [j5]Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir, Camelia Hora, Yizi Xing, Bram Kruseman:
Diagnosis of Local Spot Defects in Analog Circuits. IEEE Trans. Instrum. Meas. 61(10): 2701-2712 (2012) - 2011
- [j4]Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(12): 1911-1922 (2011) - [j3]Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Gate Leakage Impact on Full Open Defects in Interconnect Lines. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2209-2220 (2011) - [c17]Hamidreza Hashempour, Jos Dohmen, Bratislav Tasic, Bram Kruseman, Camelia Hora, Maikel van Beurden, Yizi Xing:
Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example. DATE 2011: 371-376 - [c16]Bram Kruseman, Bratislav Tasic, Camelia Hora, Jos Dohmen, Hamidreza Hashempour, Maikel van Beurden, Yizi Xing:
Defect Oriented Testing for analog/mixed-signal devices. ITC 2011: 1-10 - 2010
- [c15]Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Diagnosis of full open defects in interconnect lines with fan-out. ETS 2010: 233-238 - [c14]Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti:
Impact of Temperature on Test Quality. VLSI Design 2010: 276-281
2000 – 2009
- 2009
- [c13]Friedrich Hapke, Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel, Hamidreza Hashempour, Stefan Eichenberger, Camelia Hora, Dan Adolfsson:
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs. ITC 2009: 1-10 - 2008
- [c12]Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi:
Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality. ITC 2008: 1-10 - [c11]Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Time-dependent Behaviour of Full Open Defects in Interconnect Lines. ITC 2008: 1-10 - [c10]Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
Full Open Defects in Nanometric CMOS. VTS 2008: 119-124 - 2007
- [j2]Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud:
Extending gate-level diagnosis tools to CMOS intra-gate faults. IET Comput. Digit. Tech. 1(6): 685-693 (2007) - [c9]Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi:
Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. VTS 2007: 145-150 - [c8]Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi:
Diagnosis of Full Open Defects in Interconnecting Lines. VTS 2007: 158-166 - 2006
- [c7]Xinyue Fan, Will R. Moore, Camelia Hora, Mario Konijnenburg, Guido Gronthoud:
A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis. VTS 2006: 266-271 - 2005
- [c6]Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud:
Stuck-open fault diagnosis with stuck-at model. ETS 2005: 182-187 - [c5]Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud:
A novel stuck-at based method for transistor stuck-open fault diagnosis. ITC 2005: 9 - 2004
- [c4]Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede:
Systematic Defects in Deep Sub-Micron Technologies. ITC 2004: 290-299 - [c3]Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge:
Trends in Testing Integrated Circuits. ITC 2004: 688-697 - 2003
- [j1]Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg:
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up. J. Electron. Test. 19(4): 369-376 (2003) - [c2]Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger:
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. VTS 2003: 345-350 - 2002
- [c1]Camelia Hora, Rene Segers, Stefan Eichenberger, Maurice Lousberg:
An Effective Diagnosis Method to Support Yield Improvement. ITC 2002: 260-269
Coauthor Index
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