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ORCIDBulent I. Dervisoglu
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2000 – 2009
- 2002
[c11]Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark:
Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? VTS 2002: 445-446- 2001
- [c10]Bulent I. Dervisoglu:
A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers. DAC 2001: 53-58
1990 – 1999
- 1999
- [c9]Bulent I. Dervisoglu:
Design for testability: it is time to deliver it for Time-to-Market. ITC 1999: 1102-1111 - 1998
- [c8]Bulent I. Dervisoglu, Mike Ricchetti, William Eklow:
Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard. ITC 1998: 980-989 - 1995
- [j8]Bulent I. Dervisoglu:
Special Report: Shared-I/O Scan Test. IEEE Des. Test Comput. 12(4): 81-83 (1995) - 1994
- [c7]Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther:
Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294 - 1992
- [j7]Bulent I. Dervisoglu:
Boundary-Scan Update: IEEE P1149.2 Description and Status Report. IEEE Des. Test Comput. 9(3): 79-81 (1992) - 1991
- [j6]Bulent I. Dervisoglu:
Features of a Scan and Clock Resource chip for providing access to board-level test functions. J. Electron. Test. 2(1): 107-115 (1991) - [c6]Bulent I. Dervisoglu, Gayvin E. Stong:
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement. ITC 1991: 365-374 - [c5]Bulent I. Dervisoglu, Gayvin E. Stong:
Application of Scan-Based DFT Methodology for Detecting Static and Timing Failures in VLSI Components. VLSI 1991: 429-438 - 1990
- [j5]Bulent I. Dervisoglu:
Application of scan hardware and software for debug and diagnostics in a workstation environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(6): 612-620 (1990) - [c4]Bulent I. Dervisoglu:
Towards a standard approach for controlling board-level test functions. ITC 1990: 582-590
1980 – 1989
- 1989
- [j4]Bulent I. Dervisoglu:
Scan-path architecture for pseudorandom testing. IEEE Des. Test 6(4): 32-48 (1989) - [c3]Bulent I. Dervisoglu, M. A. Keil:
ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art Workstation. DAC 1989: 718-721 - 1988
- [c2]Bulent I. Dervisoglu:
Using Scan Technology for Debug and Diagnostics in a Workstation Environment. ITC 1988: 976-986 - 1984
- [c1]Bulent I. Dervisoglu:
On Coosing a Hardware Descriptive Language for Digital Systems Testing/Verification. ITC 1984: 184-187 - 1981
- [j3]Bulent I. Dervisoglu, Donald J. Criscione:
A Hard Progammable Control Unit Design Using VLSI Technology. IEEE Trans. Computers 30(10): 800-810 (1981) - 1980
- [j2]Bulent I. Dervisoglu, Howard A. Sholl:
Theory and Design of Mixed-Mode Sequential Machines. IEEE Trans. Computers 29(7): 639-648 (1980)
1970 – 1979
- 1974
- [j1]Bulent I. Dervisoglu:
Hardware description languages in Great Britain. Computer 7(12): 64-66 (1974) - 1973
- [b1]Bulent I. Dervisoglu:
Computer aided design techniques applied to logic design. University of Edinburgh, UK, 1973
Coauthor Index
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