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ORCIDTesting for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014
- Sandeep Kumar Goel, Krishnendu Chakrabarty:
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. CRC Press 2014, ISBN 978-1-439-82941-7 - Sudhakar M. Reddy, Peter Maxwell:
Fundamentals of Small-Delay Defect Testing. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 1-22
Section I Timing-Aware ATPG
- Duncan M. Hank Walker:
K Longest Paths. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 23-48 - Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin:
Timing-Aware ATPG. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 49-72
Section II Faster-than-at-Speed
- Nisar Ahmed, Mohammad Tehranipoor:
Faster-than-at-Speed Test for Screening Small-Delay Defects. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 73-94 - Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor:
Circuit Path Grading Considering Layout, Process Variations, and Cross Talk. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 95-118
Section III Alternative Methods
- Mahmut Yilmaz:
Output Deviations-Based SDD Testing. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 119-146 - Sandeep Kumar Goel, Narendra Devta-Prasanna:
Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 147-160 - Sandeep Kumar Goel, Krishnendu Chakrabarty:
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 161-184
Section IV SDD Metrics
- Narendra Devta-Prasanna, Sandeep Kumar Goel:
Small-Delay Defect Coverage Metrics. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 185-210
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