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ORCIDJabulani Nyathi
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2020 – today
- 2021
[j3]Saqer Alhloul
, Uri Rogers, Donald C. Richter, Jabulani Nyathi:
An experimental justification for the proportionality between the coherence bandwidth and the root mean square time delay spread using deterministic time of arrivals. Phys. Commun. 49: 101461 (2021)
2010 – 2019
- 2017
- [c14]Jabulani Nyathi, Abubaker Mutumba:
Slowing the none-critical path to improve carry look-ahead adder power dissipation. MWSCAS 2017: 890-893
2000 – 2009
- 2007
- [j2]Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Walid Ibrahim:
Serial Addition: Locally Connected Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2564-2579 (2007) - [c13]Hsiang-Ling Jamie Lin, Jabulani Nyathi, Clint Cole:
Evaluation of CPU Utilization Under a Hardware-software Partitioned Enviroment (Migrating Software to Hardware). ESA 2007: 222-228 - [c12]Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande:
Multiple clock domain synchronization for network on chip architectures. SoCC 2007: 291-294 - 2006
- [c11]Valeriu Beiu, Jabulani Nyathi, Snorre Aunet, Mawahib H. Sulieman:
Femto Joule Switching for Nano Electronics. AICCSA 2006: 415-423 - [c10]Kamini Prajapati, Jabulani Nyathi:
An Efficient Key Update Scheme For Wireless Sensor Networks. ICWN 2006: 8-14 - [c9]Jabulani Nyathi, Brent Bero:
Logic circuits operating in subthreshold voltages. ISLPED 2006: 131-134 - 2005
- [j1]José G. Delgado-Frias, Jabulani Nyathi, Suryanarayana Tatapudi:
Decoupled dynamic ternary content addressable memories. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(10): 2139-2147 (2005) - [c8]Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal:
On the Advantages of Serial Architectures for Low-Power Reliable Computations. ASAP 2005: 276-281 - [c7]Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias:
A distributed FIFO scheme for on chip communication. ISCAS (2) 2005: 1851-1854 - 2004
- [c6]James Levy, Jabulani Nyathi:
A High Performance, Low Area Overhead Carry Lookahead Adder. ESA/VLSI 2004: 417-426 - [c5]Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias:
A Distributed FIFO Scheme for System on Chip Inter-Component Communication. ESA/VLSI 2004: 536-540 - 2000
- [c4]José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan:
A wave-pipelined router architecture using ternary associative memory. ACM Great Lakes Symposium on VLSI 2000: 67-70 - [c3]José G. Delgado-Frias, Jabulani Nyathi:
A wave-pipelined CMOS associate router for communication switches. ISCAS 2000: 391-394
1990 – 1999
- 1998
- [c2]José G. Delgado-Frias, Jabulani Nyathi:
A VLSI High-Performance Encoder with Priority Lookahead. Great Lakes Symposium on VLSI 1998: 59-64 - 1996
- [c1]José G. Delgado-Frias, Jabulani Nyathi, Chester L. Miller, Douglas H. Summerville:
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. Great Lakes Symposium on VLSI 1996: 246-251
Coauthor Index
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