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ORCIDRajesh Raina
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2000 – 2009
- 2008
[c24]Rajesh Raina:
Achieving Zero-Defects for Automotive Applications. ITC 2008: 1-10- 2006
- [c23]Rajesh Raina:
What is DFM & DFY and Why Should I Care ? ITC 2006: 1-9 - 2005
- [c22]Rajesh Raina:
Is the concern for soft-error overblown? ITC 2005: 1 - [c21]Rajesh Raina:
Is the concern for soft-error overblown? ITC 2005: 2 - [c20]Rajesh Raina:
Have we overcome the challenges associated with SoC and multi-core testing? ITC 2005: 2 - [c19]Rajesh Raina:
Have we overcome the challenges associated with SoC and multi-core testing? ITC 2005: 2 - 2004
- [j2]Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida:
Skew measurements in clock distribution circuits using an analytic signal method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 997-1009 (2004) - 2002
- [c18]Mani Soma, Welela Haileselassie, Jessica Yan, Rajesh Raina:
A Wavelet-Based Timing Parameter Extraction Method. ITC 2002: 120-128 - [c17]Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina:
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. ITC 2002: 574-583 - [c16]John Gatej, Lee Song, Carol Pyron, Rajesh Raina, Tom Munns:
valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits. ITC 2002: 1040-1049 - [c15]Dawit Belete, Ashutosh Razdan, William Schwarz, Rajesh Raina, Christopher Hawkins, Jeff Morehead:
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor . ITC 2002: 1111-1119 - [c14]Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich:
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. VTS 2002: 3-8 - 2001
- [j1]Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir:
Very Low Cost Testers: Opportunities and Challenges. IEEE Des. Test Comput. 18(5): 60-69 (2001) - [c13]Takahiro J. Yamaguchi, Mani Soma, Jim Nissen, David Halter, Rajesh Raina, Masahiro Ishida:
Testing clock distribution circuits using an analytic signal method. ITC 2001: 323-331 - [c12]Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma, David Halter, Rajesh Raina, Jim Nissen:
A Method for Measuring the Cycle-to-Cycle Period Jitter of High-Frequency Clock Signals. VTS 2001: 102-110 - 2000
- [c11]Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan:
DFT advances in Motorola's Next-Generation 74xx PowerPCTM microprocessor. ITC 2000: 131-140 - [c10]Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe:
Jitter measurements of a PowerPCTM microprocessor using an analytic signal method. ITC 2000: 955-964 - [c9]Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina:
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. VTS 2000: 3-8
1990 – 1999
- 1999
- [c8]Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar:
DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. ITC 1999: 137-146 - [c7]Magdy S. Abadir, Rajesh Raina:
Design-for-test methodology for Motorola PowerPC microprocessors. ITC 1999: 810-819 - 1998
- [c6]Rajesh Raina, Robert F. Molyneaux:
Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches. Great Lakes Symposium on VLSI 1998: 222-229 - 1997
- [c5]Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh:
Efficient Testing of Clock Regenerator Circuits in Scan Designs. DAC 1997: 95-100 - [c4]Rajesh Raina, Charles Njinda, Robert F. Molyneaux:
How Seriously Do You Take Your Possible-Detect Faults? ITC 1997: 819-828 - [c3]Rajesh Raina, Jacob A. Abraham, A. K. Pujari:
T4: Verification. VLSI Design 1997: 3 - 1996
- [c2]James Monaco, David Holloway, Rajesh Raina:
Functional Verification Methodology for the PowerPC 604 Microprocessor. DAC 1996: 319-324 - 1991
- [c1]Rajesh Raina, Peter N. Marinos:
Signature Analysis with Modified Linear Feedback Shift Registers (M-LFSRs). FTCS 1991: 88-95
Coauthor Index
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