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Nandu Tendolkar
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2000 – 2009
- 2006
- [c6]Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich:
Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. ITC 2006: 1-9 - 2005
- [c5]Nandu Tendolkar, Dawit Belete, Ashutosh Razdan, Hereman Reyes, Bill Schwarz, Marie Sullivan:
Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture. ITC 2005: 9 - 2002
- [c4]Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina:
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture. ITC 2002: 574-583 - [c3]Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich:
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. VTS 2002: 3-8 - 2000
- [c2]Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina:
At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. VTS 2000: 3-8
1990 – 1999
- 1999
- [c1]Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar:
DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. ITC 1999: 137-146
Coauthor Index
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