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ORCIDIbrahim N. Hajj
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2010 – 2019
- 2017
[c74]Ibrahim N. Hajj:
Beyond SPICE. ISCAS 2017: 1- 2015
- [j27]Ibrahim N. Hajj:
On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(3): 495-499 (2015) - 2012
- [j26]Ibrahim N. Hajj:
Extended Nodal Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(1): 89-100 (2012)
2000 – 2009
- 2004
- [j25]Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Postroute gate sizing for crosstalk noise reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1670-1677 (2004) - 2003
- [j24]Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj:
Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 337-345 (2003) - [c73]Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957 - [c72]Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj:
Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176 - 2002
- [j23]Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj:
Estimation of state line statistics in sequential circuits. ACM Trans. Design Autom. Electr. Syst. 7(3): 455-473 (2002) - [j22]Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm:
A technique for Improving dual-output domino logic. IEEE Trans. Very Large Scale Integr. Syst. 10(4): 508-511 (2002) - [c71]Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj:
Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE 2002: 456-463 - [c70]Geng Bai, Ibrahim N. Hajj:
Simultaneous Switching Noise and Resonance Analysis of On-Chip Power Distribution Network. ISQED 2002: 163-168 - [c69]Murat R. Becer, Rajendran Panda, David T. Blaauw, Ibrahim N. Hajj:
Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED 2002: 413-418 - [c68]Murat R. Becer, David T. Blaauw, Ibrahim N. Hajj, Rajendran Panda:
Early probabilistic noise estimation for capacitively coupled interconnects. SLIP 2002: 77-83 - 2001
- [c67]Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits. DAC 2001: 295-300 - [c66]Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
Maximum power supply noise estimation in VLSI circuits using multimodal genetic algorithms. ICECS 2001: 1437-1440 - [c65]Sudhakar Bobba, Ibrahim N. Hajj:
Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits. ISCAS (5) 2001: 195-198 - [c64]Sudhakar Bobba, Ibrahim N. Hajj:
Maximum voltage variation in the power distribution network of VLSI circuits with RLC models. ISLPED 2001: 376-381 - [c63]Ninglong Lu, Ibrahim N. Hajj:
A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model. ISQED 2001: 133-138 - [c62]Murat R. Becer, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj:
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED 2001: 158-163 - [c61]Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. ISQED 2001: 205-210 - [c60]Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
RC Power Bus Maximum Voltage Drop in Digital VLSI Circuits. ISQED 2001: 257-258 - 2000
- [j21]Nikolaos Bellas
, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George I. Stamoulis:
Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 8(3): 317-326 (2000) - [j20]Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos:
Using dynamic cache management techniques to reduce energy in general purpose processors. IEEE Trans. Very Large Scale Integr. Syst. 8(6): 693-708 (2000) - [c59]Sudhakar Bobba, Ibrahim N. Hajj:
High-performance bidirectional repeaters. ACM Great Lakes Symposium on VLSI 2000: 53-58 - [c58]Sudhakar Bobba, Ibrahim N. Hajj:
Peak current estimation for digital filters. ICASSP 2000: 3251-3254 - [c57]Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
Simulation and Optimization of the Power Distribution Network in VLSI Circuits. ICCAD 2000: 481-486 - [c56]Sudhakar Bobba, Ibrahim N. Hajj:
Current-Mode Threshold Logic Gates. ICCD 2000: 235-240 - [c55]Mohammad M. Mansour, Makram M. Mansour, Ibrahim N. Hajj, Naresh R. Shanbhag:
Instruction scheduling for low power on dynamically variable voltage processors. ICECS 2000: 613-618 - [c54]Murat R. Becer, Ibrahim N. Hajj:
An analytical model for delay and crosstalk estimation in interconnects under general switching conditions. ICECS 2000: 831-834 - [c53]Ninglong Lu, Ibrahim N. Hajj:
A hierarchical based approach for coupling aware delay analysis of combinational logic blocks. ICECS 2000: 1012-1015 - [c52]Murat R. Becer, Ibrahim N. Hajj:
An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling. ISQED 2000: 51-58 - [c51]Geng Bai, Sudhakar Bobba, Ibrahim N. Hajj:
Power Bus Maximum Voltage Drop in Digital VLSI Circuits. ISQED 2000: 263-268
1990 – 1999
- 1999
- [j19]Andreas G. Veneris, Ibrahim N. Hajj:
Design error diagnosis and correction via test vector simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12): 1803-1816 (1999) - [j18]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
A coding framework for low-power address and data busses. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 212-221 (1999) - [j17]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Information-theoretic bounds on average signal transition activity [VLSI systems]. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 359-368 (1999) - [c50]Ninglong Lu, Ibrahim N. Hajj:
An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications. Great Lakes Symposium on VLSI 1999: 68- - [c49]Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos, George D. Stamoulis:
Energy and Performance Improvements in Microprocessor Design Using a Loop Cache. ICCD 1999: 378-383 - [c48]Andreas G. Veneris, Ibrahim N. Hajj:
A hybrid approach to design error detection and correction [VLSI digital circuits]. ICECS 1999: 347-350 - [c47]Andreas G. Veneris, Ibrahim N. Hajj:
Correcting multiple design errors in digital VLSI circuits. ISCAS (1) 1999: 31-34 - [c46]Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos:
An analytical, transistor-level energy model for SRAM-based caches. ISCAS (6) 1999: 198-201 - [c45]Ninglong Lu, Ibrahim N. Hajj:
A reduced-order scheme for coupled lumped-distributed interconnect simulation. ISCAS (6) 1999: 250-253 - [c44]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Low-power distributed arithmetic architectures using nonuniform memory partitioning. ISCAS (3) 1999: 470-473 - [c43]Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos:
Using dynamic cache management techniques to reduce energy in a high-performance processor. ISLPED 1999: 64-69 - [c42]Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm:
An optimization technique for dual-output domino logic. ISLPED 1999: 258-260 - [c41]Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag:
Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. VLSI Design 1999: 358- - [c40]Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venkataraman, W. Kent Fuchs:
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits. VTS 1999: 58-63 - 1998
- [c39]Sudhakar Bobba, Ibrahim N. Hajj:
Maximum Current Estimation in Programmable Logic Arrays. Great Lakes Symposium on VLSI 1998: 301-306 - [c38]Nikolaos Bellas, Ibrahim N. Hajj, George D. Stamoulis, Constantine D. Polychronopoulos:
Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. ISLPED 1998: 70-75 - [c37]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Decorrelating (DECOR) transformations for low-power adaptive filters. ISLPED 1998: 250-255 - [c36]Sudhakar Bobba, Ibrahim N. Hajj:
Estimation of maximum current envelope for power bus analysis and design. ISPD 1998: 141-146 - [c35]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. VLSI Design 1998: 18-23 - 1997
- [j16]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Analytical estimation of signal transition activity from word-level statistics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(7): 718-733 (1997) - [j15]Pi-Yu Chung, Ibrahim N. Hajj:
Diagnosis and correction of multiple logic design errors in digital circuits. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 233-237 (1997) - [c34]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Analytical Estimation of Transition Activity From Word-Level Signal Statistics. DAC 1997: 582-587 - [c33]Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj:
Monte-Carlo approach for power estimation in sequential circuits. ED&TC 1997: 416-420 - [c32]Andreas G. Veneris, Ibrahim N. Hajj:
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. Great Lakes Symposium on VLSI 1997: 45-50 - [c31]Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
Achievable bounds on signal transition activity. ICCAD 1997: 126-129 - [c30]Tzuhao Chen, Ibrahim N. Hajj:
GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/IDDQ testing environment. ICCAD 1997: 555-561 - 1996
- [j14]Ping-Chung Li, Ibrahim N. Hajj:
Computer-aided redesign of VLSI circuits for hot-carrier reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 453-464 (1996) - [c29]Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel:
Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. VTS 1996: 456-462 - 1995
- [j13]Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj:
Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 308-320 (1995) - [j12]Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs:
Circuit-level dictionaries of CMOS bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 596-603 (1995) - [j11]Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj:
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 998-1012 (1995) - [c28]Farid N. Najm, Shashank Goel, Ibrahim N. Hajj:
Power Estimation in Sequential Circuits. DAC 1995: 635-640 - 1994
- [j10]Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj:
A probabilistic timing approach to hot-carrier effect estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(10): 1223-1234 (1994) - [j9]Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj:
Logic design error diagnosis and correction. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 320-332 (1994) - [c27]Weitong Chuang, Ibrahim N. Hajj:
Delay and area optimization for compact placement by gate resizing and relocation. ICCAD 1994: 145-148 - [c26]Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj:
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits. ISCAS 1994: 435-438 - [c25]Terry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs:
Circuit-level dictionaries of CMOS bridging faults. VTS 1994: 386-391 - 1993
- [j8]Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj:
Switch-level timing simulation of bipolar ECL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4): 516-530 (1993) - [c24]Georgios I. Stamoulis, Ibrahim N. Hajj:
Improved Techniques for Probabilistic Simulation Including Signal Correlation Effects. DAC 1993: 379-383 - [c23]Harish Kriplani, Farid N. Najm, Ping Yang, Ibrahim N. Hajj:
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits. DAC 1993: 384-388 - [c22]Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj:
Diagnosis and Correction of Logic Design Errors in Digital Circuits. DAC 1993: 503-508 - [c21]Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj:
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. ICCAD 1993: 220-223 - [c20]Ping-Chung Li, Ibrahim N. Hajj:
Computer-Aided Redesign of VLSI Circuits for Hot-Carrier Reliability. ICCD 1993: 534-537 - [c19]Weitong Chuang, Ibrahim N. Hajj:
Fast Mixed-Mode Simulation for Accurate MOS Bridging Fault Detection. ISCAS 1993: 1503-1506 - [c18]Pi-Yu Chung, Ibrahim N. Hajj, Janak H. Patel:
Efficient Variable Ordering Heuristics for Shared ROBDD. ISCAS 1993: 1690-1693 - 1992
- [c17]Harish Kriplani, Farid N. Najm, Ibrahim N. Hajj:
Maximum Current Estimation in CMOS Circuits. DAC 1992: 2-7 - [c16]Ping-Chung Li, Georgios I. Stamoulis, Ibrahim N. Hajj:
A probabilistic timing approach to hot-carrier effect estimation. ICCAD 1992: 210-213 - [c15]Pi-Yu Chung, Ibrahim N. Hajj:
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits. ITC 1992: 742-751 - [c14]Ibrahim N. Hajj, Terry Lee:
Simulation of physical faults in VLSI circuits. VTS 1992: 202-207 - 1991
- [j7]Farid N. Najm, Ibrahim N. Hajj, Ping Yang:
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(11): 1372-1381 (1991) - [c13]Terry Lee, Ibrahim N. Hajj:
A Switch-Level Matrix Approach to Transistor-Level Fault Simulation. ICCAD 1991: 554-557 - 1990
- [j6]P. Gee, Min-You Wu, S. M. Kang, Ibrahim N. Hajj:
A metal - metal matrix cell generator for multi-level metal MOS technology. Integr. 9(1): 25-47 (1990) - [j5]Ibrahim N. Hajj, Stig Skelboe:
A multilevel parallel solver for block tridiagonal and banded linear systems. Parallel Comput. 15(1-3): 21-45 (1990) - [j4]Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj:
Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 439-450 (1990) - [j3]Farid N. Najm, Ibrahim N. Hajj:
The complexity of fault detection in MOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(9): 995-1001 (1990) - [c12]Ibrahim N. Hajj:
An Algebra for Switch-Level Simulation. ICCAD 1990: 488-491 - [c11]Young-Hyun Jun, Ibrahim N. Hajj, Sang-Heon Lee, Song-Bai Park:
High speed VLSI logic simulation using bitwise operations and parallel processing. ICCD 1990: 171-174
1980 – 1989
- 1989
- [j2]Min-You Wu, Ibrahim N. Hajj:
Switching network logic approach to sequential MOS circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(7): 782-794 (1989) - [c10]David Overhauser, Ibrahim N. Hajj, Yi-Fan Hsu:
Automatic mixed-mode timing simulation. ICCAD 1989: 84-87 - [c9]P. Gee, Ibrahim N. Hajj, Sung-Mo Kang:
A custom cell generation system for double-metal CMOS technology. ICCAD 1989: 140-143 - [c8]Farid N. Najm, Ibrahim N. Hajj, Ping Yang:
Computation of bus current variance for reliability estimation of VLSI circuits. ICCAD 1989: 202-205 - [c7]Daniel G. Saab, Ibrahim N. Hajj, Joseph T. Rahmeh:
Parallel-concurrent fault simulation. ICCD 1989: 298-301 - [c6]Farid N. Najm, Ibrahim N. Hajj, Ping Yang:
Electromigration median time-to-failure based on a stochastic current waveform. ICCD 1989: 447-450 - 1988
- [c5]Daniel G. Saab, Andrew T. Yang, Ibrahim N. Hajj:
Delay Modeling and Time of Bipolar Digital Circuits. DAC 1988: 288-293 - [c4]Tat-Kwan Yu, Sung-Mo Kang, Ibrahim N. Hajj, Timothy N. Trick:
iEDISON: an interactive statistical design tool for MOS VLSI circuits. ICCAD 1988: 20-23 - [c3]David Overhauser, Ibrahim N. Hajj:
A tabular macromodeling approach to fast timing simulation including parasitics. ICCAD 1988: 70-73 - [c2]Farid N. Najm, Richard Burch, Ping Yang, Ibrahim N. Hajj:
CREST-a current estimator for CMOS circuits. ICCAD 1988: 204-207 - [c1]Mi-Chang Chang, Ibrahim N. Hajj:
iPRIDE: a parallel integrated circuit simulator using direct method. ICCAD 1988: 304-307 - 1987
- [j1]Ibrahim N. Hajj, Daniel G. Saab:
Switch-Level Logic Simulation of Digital Bipolar Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(2): 251-258 (1987)
Coauthor Index
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