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"Timing and area optimization for standard-cell VLSI circuit design."

Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj (1995)

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DOI: 10.1109/43.365122

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - journals/tcad/ChuangSH95
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  persistent URL:
  - https://dblp.org/rec/journals/tcad/ChuangSH95
Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj:
Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 308-320 (1995)

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