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ORCID7. Great Lakes Symposium on VLSI 1997: Urbana, IL, USA
- 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 13-15 March 1997, Urbana, IL, USA. IEEE Computer Society 1997, ISBN 0-8186-7904-2
Physical Design
- Yuichiro Takei, Akira Onozawa, Kenji Kawai, Hitoshi Kitazawa:
An Efficient Paired-net Routing Algorithm for High-speed Bipolar LSIs. 2-7 - Elizabeth J. Brauer, Pradeep Elamanchili:
A Full-Swing Bootstrapped BiCMOS Buffer. 8-13 - João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije:
A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems. 14-
Testing I
- Irith Pomeranz, Sudhakar M. Reddy:
On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. 20-25 - Musaed A. Al-Kharji, Sami A. Al-Arian:
A New Heuristic Algorithm for Estimating Signal and Detection Probabilities. 26-31 - Cristiana Bolchini, Fabio Salice, Donatella Sciuto:
Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks. 32-
Synthesis and Verification
- Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya:
Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. 39-44 - Andreas G. Veneris, Ibrahim N. Hajj:
A Fast Algorithm for Locating and Correcting Simple Design Errors in VLSI Digital Circuits. 45-50 - Josef Fleischmann, Rolf Schlagenhaft, Martin Peller, Norbert Fröhlich:
OLIVIA: Objectoriented Logicsimulation Implementing the VITAL Standard. 51-
High-Level Design Methodologies
- Adel Baganne, Jean Luc Philippe, Eric Martin:
Hardware interface design for real time embedded systems. 58-63 - Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Bill Lin, Hugo De Man, Gjalt G. de Jong:
A System Design Methodology for Telecommunication Network Applications. 64-69 - Antonio Lioy, Enrico Macii, Massimo Poncino, Massimo Rossello:
Accurate Entropy Calculation for Large Logic Circuits Based on Output Clustering. 70-
Low-Power Design
- Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano:
Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. 77-82 - Shaoyi Wang:
Power Reduction in Large Fan-in CMOS Gates in Logic Arrays Using Selective Precharge. 83-85 - Hanho Lee, Gerald E. Sobelman:
A New Low-Voltage Full Adder Circuit. 88-
VLSI Architecture I
- Fabio Ancona, Giorgio Oddone, Stefano Rovetta, Gianni Uneddu, Rodolfo Zunino:
VLSI Architectures for Programmable Sorting of Analog Quantities with Multiple-Chip Support. 94-99 - Sam S. Appleton, Shannon V. Morton, Michael J. Liebelt
:
A new method for asynchronous pipeline control. 100-104 - Kevin P. Acken, Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin:
The MGAP Family of Processor Arrays. 105-
Testing II
- H.-Ch. Dahmen, Uwe Gläser, Heinrich Theodor Vierhaus:
An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation. 112-117 - Franco Fummi, Mariagiovanna Sami, F. Tartarini:
Use of Statecharts-Related Description to Achieve Testable Design of Control Subsystems. 118-123 - Giacomo Buonanno, Fabrizio Ferrandi, L. Ferrandi, Franco Fummi, Donatella Sciuto:
How an "Evolving" Fault Model Improves the Behavioral Test Generation. 124-
Applications
- Michael Weeks, M. B. Maaz, H. Krishnamurthy, Paul Shipley, Magdy A. Bayoumi:
A prototype chipset for a large scaleable ATM switching node. 131-136 - Elizabeth J. Brauer, Ranu Jung, Denise M. Wilson, James J. Abbas:
Analog Circuit Model of Lamprey Unit Pattern Generator. 137-142 - Ali Assi, Mohamad Sawan, Rabin Raut:
A New CMOS Tunable Transconductor Dedicated to VHF Continuous-Time Filters. 143-
High-Level Synthesis
- Sissades Tongsima, Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Nelson L. Passos:
Scheduling with Confidence for Probabilistic Data-flow Graphs. 150-155 - Raghava V. Cherabuddi, Magdy A. Bayoumi, H. Krishnamurthy:
A low power based system partitioning and binding technique for multi-chip module architectures. 156-162 - Ted Zhihong Yu, Edwin Hsing-Mean Sha, Nelson L. Passos, Roy Dz-Ching Ju:
Algorithm and Hardware Support for Branch Anticipation. 163-
VLSI Architecture II
- Sergio D'Angelo, Lauro Mantoani, Riccardo P. G. Mazzei, Stefania Russo, Giacomo R. Sechi:
Modular Design of Communication Node Prototypes. 170-175 - Fabio Ancona, Alessandro De Gloria, Rodolfo Zunino:
Parallel VLSI Architectures for Cryptographic Systems. 176-181 - Eric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin:
A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines. 182-
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