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2020 – today
- 2022
[j7]Trishit Ruj
, Goro Komatsu, Gene Schmidt, Suniti Karunatillake, Kenji Kawai:
Tectonism of Late Noachian Mars: Surface Signatures from the Southern Highlands. Remote. Sens. 14(22): 5664 (2022)
2010 – 2019
- 2015
- [c5]Hiroyuki Uzawa, Yuki Arikawa, Kenji Kawai, Satoshi Shigematsu:
Data transmission scheme for enhancing effective downlink bandwidth in 5G mobile fronthaul with TDM-PON. ECOC 2015: 1-3 - [c4]Yuki Arikawa, Kenji Kawai, Hiroyuki Uzawa, Satoshi Shigematsu:
Practical resource scheduling in massive-cell deployment for 5G mobile communications systems. ISPACS 2015: 456-461 - 2011
- [j6]Keigo Hikishima, M. M. Quallo, Yuki Komaki, Masayuki Yamada, Kenji Kawai, Suketaka Momoshima, Hirotaka James Okano, Erika Sasaki, N. Tamaoki, R. N. Lemon, Atsushi Iriki, Hideyuki Okano:
Population-averaged standard template brain atlas for the common marmoset (Callithrix jacchus). NeuroImage 54(4): 2741-2749 (2011) - 2010
- [c3]Yukikuni Nishida, Kenji Kawai, Keiichi Koike:
A 2Gb/s network processor with a 24mW IPsec offload for residential gateways. ISSCC 2010: 280-281
2000 – 2009
- 2005
- [j5]Kazuhiko Terada, Kenji Kawai, Osamu Ishida, Keiji Kishine, Noboru Iwasaki, Haruhiko Ichino:
Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks. IEICE Trans. Commun. 88-B(10): 3952-3961 (2005) - 2000
- [j4]Satoru Okamoto, Masafumi Koga, Hiro Suzuki, Kenji Kawai:
Robust photonic transport network implementation with optical cross-connect systems. IEEE Commun. Mag. 38(3): 94-103 (2000) - [j3]Kenji Kawai, Haruhiko Ichino:
A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI. IEEE J. Solid State Circuits 35(12): 1988-1991 (2000)
1990 – 1999
- 1999
- [j2]Kenji Kawai, Keiichi Koike, Yuichiro Takei, Akira Onozawa, Hitoshi Obara, Haruhiko Ichino:
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. IEEE J. Solid State Circuits 34(1): 12-17 (1999) - 1998
- [j1]Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino:
High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. IEEE J. Solid State Circuits 33(10): 1536-1544 (1998) - 1997
- [c2]Yuichiro Takei, Akira Onozawa, Kenji Kawai, Hitoshi Kitazawa:
An Efficient Paired-net Routing Algorithm for High-speed Bipolar LSIs. Great Lakes Symposium on VLSI 1997: 2-7 - 1995
- [c1]Akira Onozawa, Hitoshi Kitazawa, Kenji Kawai:
Post-layout optimization of power and timing for ECL LSIs. ED&TC 1995: 167-172
Coauthor Index
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