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ORCIDKia Bazargan
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- affiliation: University of Minnesota, USA
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2020 – today
- 2024
[j30]Alireza Khataei
, Gaurav Singh, Kia Bazargan:
SimBU: Self-Similarity-Based Hybrid Binary-Unary Computing for Nonlinear Functions. IEEE Trans. Computers 73(9): 2192-2205 (2024)- [c67]Alireza Khataei, Kia Bazargan:
CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond. FPGA 2024: 2-11 - 2023
- [c66]Alireza Khataei, Gaurav Singh, Kia Bazargan:
Optimizing Hybrid Binary-Unary Hardware Accelerators Using Self-Similarity Measures. FCCM 2023: 105-113 - [c65]Alireza Khataei, Gaurav Singh, Kia Bazargan:
Approximate Hybrid Binary-Unary Computing with Applications in BERT Language Model and Image Processing. FPGA 2023: 165-175 - [c64]Alireza Khataei, Kia Bazargan:
Constant Coefficient Multipliers Using Self-Similarity-Based Hybrid Binary-Unary Computing. ICCAD 2023: 1-7 - 2022
- [j29]S. Rasoul Faraji, Pierre Abillama, Kia Bazargan:
Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 15(3): 29:1-29:25 (2022) - 2020
- [j28]S. Rasoul Faraji, Kia Bazargan:
Hybrid Binary-Unary Hardware Accelerator. IEEE Trans. Computers 69(9): 1308-1319 (2020) - [j27]Soheil Mohajer, Zhiheng Wang, Kia Bazargan, Yuyang Li:
Parallel Unary Computing Based on Function Derivatives. ACM Trans. Reconfigurable Technol. Syst. 14(1): 4:1-4:25 (2020) - [j26]Zhiheng Wang, Devan Larso, Morgen Barker, Soheil Mohajer, Kia Bazargan:
Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel. IEEE Trans. Very Large Scale Integr. Syst. 28(8): 1821-1832 (2020) - [c63]S. Rasoul Faraji, Pierre Abillama, Kia Bazargan:
Low-Cost Approximate Constant Coefficient Hybrid Binary-Unary Multiplier for DSP Applications. FCCM 2020: 93-101 - [c62]S. Rasoul Faraji, Kia Bazargan:
Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs. ICCAD 2020: 123:1-123:9 - [c61]S. Rasoul Faraji, Pierre Abillama, Gaurav Singh, Kia Bazargan:
HBUCNNA: Hybrid Binary-Unary Convolutional Neural Network Accelerator. ISCAS 2020: 1-5 - [c60]M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja:
Energy-Efficient Pulse-Based Convolution for Near-Sensor Processing. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [c59]M. Hassan Najafi, S. Rasoul Faraji, Kia Bazargan, David J. Lilja:
Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing. ASAP 2019: 36 - [c58]S. Rasoul Faraji, Kia Bazargan:
Hybrid binary-unary hardware accelerator. ASP-DAC 2019: 210-215 - [c57]S. Rasoul Faraji, M. Hassan Najafi, Bingzhe Li, David J. Lilja, Kia Bazargan:
Energy-Efficient Convolutional Neural Networks with Deterministic Bit-Stream Processing. DATE 2019: 1757-1762 - [c56]Sayed Abdolrasouol Faraji, Gaurav Singh, Kia Bazargan:
HBUNN - Hybrid Binary-Unary Neural Network: Realizing a Complete CNN on an FPGA. ICCD 2019: 156-163 - [c55]M. Hassan Najafi, S. Rasoul Faraji, Bingzhe Li, David J. Lilja, Kia Bazargan:
Accelerating Deterministic Bit-Stream Computing with Resolution Splitting. ISQED 2019: 157-162 - [e2]Kia Bazargan, Stephen Neuendorffer:
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2019, Seaside, CA, USA, February 24-26, 2019. ACM 2019, ISBN 978-1-4503-6137-8 [contents] - 2018
- [j25]M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan:
Low-Cost Sorting Network Circuits Using Unary Processing. IEEE Trans. Very Large Scale Integr. Syst. 26(8): 1471-1480 (2018) - [c54]Zhiheng Wang, Soheil Mohajer, Kia Bazargan:
Low latency parallel implementation of traditionally-called stochastic circuits using deterministic shuffling networks. ASP-DAC 2018: 337-342 - [c53]Soheil Mohajer, Zhiheng Wang, Kia Bazargan:
Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded Data. FPGA 2018: 77-86 - [e1]Jason Helge Anderson, Kia Bazargan:
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2018, Monterey, CA, USA, February 25-27, 2018. ACM 2018 [contents] - 2017
- [j24]M. Hassan Najafi, Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel:
A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing. ACM J. Emerg. Technol. Comput. Syst. 13(4): 57:1-57:28 (2017) - [j23]M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani:
An Overview of Time-Based Computing with Stochastic Constructs. IEEE Micro 37(6): 62-71 (2017) - [j22]M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan:
Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits. IEEE Trans. Computers 66(10): 1734-1746 (2017) - [j21]Zhiheng Wang, Ryan N. Goh, Kia Bazargan, Arnd Scheel, Naman Saraf:
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 747-759 (2017) - [j20]M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani:
Time-Encoded Values for Highly Efficient Stochastic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 25(5): 1644-1657 (2017) - [c52]M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan:
Power and Area Efficient Sorting Networks Using Unary Processing. ICCD 2017: 125-128 - [c51]Naman Saraf, Kia Bazargan:
A memory optimized mersenne-twister random number generator. MWSCAS 2017: 639-642 - 2016
- [c50]M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan:
Polysynchronous stochastic circuits. ASP-DAC 2016: 492-498 - [c49]Nimish Agashiwala, Satya Prakash Upadhyay, Kia Bazargan:
t-QuadPlace: Timing Driven Quadratic Placement using Quadrisection Partitioning for FPGAs (Abstact Only). FPGA 2016: 284 - [c48]Naman Saraf, Kia Bazargan:
Polynomial Arithmetic Using Sequential Stochastic Logic. ACM Great Lakes Symposium on VLSI 2016: 245-250 - 2015
- [j19]Divya Mahajan, Kartik Ramkrishnan, Rudra Jariwala, Amir Yazdanbakhsh, Jongse Park, Bradley Thwaites, Anandhavel Nagendrakumar, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan:
Axilog: Abstractions for Approximate Hardware Design and Reuse. IEEE Micro 35(5): 16-30 (2015) - [c47]Zhiheng Wang, Naman Saraf, Kia Bazargan, Arnd Scheel:
Randomness meets feedback: stochastic implementation of logistic map dynamical system. DAC 2015: 132:1-132:7 - [c46]Amir Yazdanbakhsh, Divya Mahajan, Bradley Thwaites, Jongse Park, Anandhavel Nagendrakumar, Sindhuja Sethuraman, Kartik Ramkrishnan, Nishanthi Ravindran, Rudra Jariwala, Abbas Rahimi, Hadi Esmaeilzadeh, Kia Bazargan:
Axilog: language support for approximate hardware design. DATE 2015: 812-817 - 2014
- [j18]Peng Li, David J. Lilja, Weikang Qian, Marc D. Riedel, Kia Bazargan:
Logical Computation on Stochastic Bit Streams with Linear Finite-State Machines. IEEE Trans. Computers 63(6): 1474-1486 (2014) - [j17]Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel:
Computation on Stochastic Bit Streams Digital Image Processing Case Studies. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 449-462 (2014) - [c45]Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel:
IIR filters using stochastic arithmetic. DATE 2014: 1-6 - [c44]Yanzi Zhu, Peiran Suo, Kia Bazargan:
Binary stochastic implementation of digital logic. FPGA 2014: 171-180 - 2013
- [c43]Naman Saraf, Kia Bazargan:
Sequential logic to transform probabilities. ICCAD 2013: 732-738 - [c42]Naman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel:
Stochastic functions using sequential logic. ICCD 2013: 507-510 - 2012
- [c41]Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja:
The synthesis of linear Finite State Machine-based Stochastic Computational Elements. ASP-DAC 2012: 757-762 - [c40]Weikang Qian, Chen Wang, Peng Li, David J. Lilja, Kia Bazargan, Marc D. Riedel:
An efficient implementation of numerical integration using logical computation on stochastic bit streams. ICCAD 2012: 156-162 - [c39]Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel:
The synthesis of complex arithmetic computation on stochastic bit streams using sequential logic. ICCAD 2012: 480-487 - [c38]Peng Li, Weikang Qian, David J. Lilja, Kia Bazargan, Marc D. Riedel:
Case Studies of Logical Computation on Stochastic Bit Streams. PATMOS 2012: 235-244 - 2011
- [j16]Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, David J. Lilja:
An Architecture for Fault-Tolerant Computation with Stochastic Logic. IEEE Trans. Computers 60(1): 93-105 (2011) - [c37]Hossein Omidian Savarbaghi, Kia Bazargan:
FPGA placement by graph isomorphism (abstract only). FPGA 2011: 284 - 2010
- [j15]Pongstorn Maidee, Kia Bazargan:
Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(12): 1870-1883 (2010) - [c36]Pongstorn Maidee, Kia Bazargan:
A fast SPFD-based rewiring technique. ASP-DAC 2010: 55-60
2000 – 2009
- 2009
- [j14]Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan:
Fast and Accurate Statistical Criticality Computation Under Process Variations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 350-363 (2009) - [c35]Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan:
A tileable switch module architecture for homogeneous 3D FPGAs. 3DIC 2009: 1-4 - [c34]Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan:
Using randomization to cope with circuit uncertainty. DATE 2009: 815-820 - [c33]Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja:
A reconfigurable stochastic architecture for highly reliable computing. ACM Great Lakes Symposium on VLSI 2009: 315-320 - [c32]Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja:
The synthesis of combinational logic to generate probabilities. ICCAD 2009: 367-374 - [c31]Satish Sivaswamy, Kia Bazargan, Marc D. Riedel:
Estimation and optimization of reliability of noisy digital circuits. ISQED 2009: 213-219 - 2008
- [j13]Satish Sivaswamy, Kia Bazargan:
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 1(1): 4:1-4:35 (2008) - [c30]Pongstorn Maidee, Nagib Hakim, Kia Bazargan:
FPGA family composition and effects of specialized blocks. FPL 2008: 101-106 - [c29]Hushrav Mogal, Kia Bazargan:
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. ICCAD 2008: 302-305 - [r2]Kia Bazargan:
FPGA Technology Mapping, Placement, and Routing. Handbook of Algorithms for Physical Design Automation 2008 - [r1]Kia Bazargan, Sachin S. Sapatnekar:
Physical Design for Three-Dimensional Circuits. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j12]Kia Bazargan, André DeHon:
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 201-202 (2007) - [c28]Hushrav Mogal, Kia Bazargan:
Microarchitecture floorplanning for sub-threshold leakage reduction. DATE 2007: 1238-1243 - [c27]Satish Sivaswamy, Kia Bazargan:
Variation-aware routing for FPGAs. FPGA 2007: 71-79 - [c26]Pongstorn Maidee, Kia Bazargan:
A generalized and unified SPFD-based rewiring technique. FPL 2007: 305-310 - [c25]Satish Sivaswamy, Kia Bazargan:
Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs. FPL 2007: 429-434 - [c24]Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan:
Clustering based pruning for statistical criticality computation under process variations. ICCAD 2007: 340-343 - 2006
- [j11]Cristinel Ababei, Kia Bazargan:
Non-contiguous linear placement for reconfigurable fabrics. Int. J. Embed. Syst. 2(1/2): 86-94 (2006) - [j10]Cristinel Ababei, Hushrav Mogal, Kia Bazargan:
Three-dimensional place and route for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1132-1140 (2006) - [j9]Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh:
Statistical Analysis and Design of HARP FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2088-2102 (2006) - [c23]Pongstorn Maidee, Kia Bazargan:
Defect-Tolerant FPGA Architecture Exploration. FPL 2006: 1-6 - 2005
- [j8]Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar:
Placement and Routing in 3D Integrated Circuits. IEEE Des. Test Comput. 22(6): 520-531 (2005) - [j7]Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan:
A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory. J. Comput. Sci. Technol. 20(5): 596-606 (2005) - [j6]Pongstorn Maidee, Cristinel Ababei, Kia Bazargan:
Timing-driven partitioning-based placement for island style FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 395-406 (2005) - [c22]Cristinel Ababei, Hushrav Mogal, Kia Bazargan:
Three-dimensional place and route for FPGAs. ASP-DAC 2005: 773-778 - [c21]Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh:
HARP: hard-wired routing pattern FPGAs. FPGA 2005: 21-29 - [c20]Cristinel Ababei, Hushrav Mogal, Kia Bazargan:
3D FPGAs: placement, routing, and architecture evaluation (abstract only). FPGA 2005: 263 - 2004
- [j5]John C. Lach, Kia Bazargan:
Editorial: Special issue on dynamically adaptable embedded systems. ACM Trans. Embed. Comput. Syst. 3(2): 233-236 (2004) - [c19]Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan:
Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory. Asia-Pacific Computer Systems Architecture Conference 2004: 88-101 - [c18]Cristinel Ababei, Pongstorn Maidee, Kia Bazargan:
Exploring Potential Benefits of 3D FPGA Integration. FPL 2004: 874-880 - [c17]Cristinel Ababei, Kia Bazargan:
Non-Contiguous Linear Placement for Reconfigurable Fabrics. IPDPS 2004 - 2003
- [c16]Pongstorn Maidee, Cristinel Ababei, Kia Bazargan:
Fast timing-driven partitioning-based placement for island style FPGAs. DAC 2003: 598-603 - [c15]Wonjoon Choi, Kia Bazargan:
Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration. DATE 2003: 11104-11105 - [c14]Karthikeyan Bhasyam, Kia Bazargan:
HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming. DSD 2003: 264-271 - [c13]Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan:
Linear Placement for Static / Dynamic Reconfiguration in JBits. FCCM 2003: 300-301 - [c12]Cristinel Ababei, Kia Bazargan:
Placement Method Targeting Predictability Robustness and Performance. ICCAD 2003: 81-85 - [c11]Wonjoon Choi, Kia Bazargan:
Incremental Placement for Timing Optimization. ICCAD 2003: 463-466 - [c10]Cristinel Ababei, Kia Bazargan:
Timing Minimization by Statistical Timing hMetis-based Partitioning. VLSI Design 2003: 58-63 - 2002
- [c9]Jinghuan Chen, Jaekyun Moon, Kia Bazargan:
A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator. DAC 2002: 349-354 - [c8]Cristinel Ababei, Kia Bazargan:
Statistical Timing Driven Partitioning for VLSI Circuits. DATE 2002: 1109 - [c7]Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis:
Multi-objective circuit partitioning for cutsize and path-based delay minimization. ICCAD 2002: 181-185 - 2001
- [j4]Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh:
Fast floorplanning for effective prediction and construction. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 341-351 (2001) - [c6]Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh:
Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures. DAC 2001: 635-640 - 2000
- [j3]Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh:
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. Des. Autom. Embed. Syst. 5(3-4): 329-338 (2000) - [j2]Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh:
Fast Template Placement for Reconfigurable Computing Systems. IEEE Des. Test Comput. 17(1): 68-83 (2000) - [c5]Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh:
A C to Hardware/Software Compiler. FCCM 2000: 331-332 - [c4]Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh:
Fast and accurate estimation of floorplans in logic/high-level synthesis. ACM Great Lakes Symposium on VLSI 2000: 95-100 - [c3]Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh:
Fast Hierarchical Floorplanning with Congestion and Timing Control. ICCD 2000: 357-362
1990 – 1999
- 1999
- [j1]Kia Bazargan, Samjung Kim, Majid Sarrafzadeh:
Nostradamus: a floorplanner of uncertain designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 389-397 (1999) - [c2]Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh:
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. IEEE International Workshop on Rapid System Prototyping 1999: 38- - 1998
- [c1]Kia Bazargan, Samjung Kim, Majid Sarrafzadeh:
Nostradamus: a floorplanner of uncertain design. ISPD 1998: 18-23
Coauthor Index
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last updated on 2024-09-10 02:09 CEST by the dblp team
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