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2020 – today
- 2024
[j6]Tianpei Zhang
, Zhenping Yin, Yubin Wei, Yaru Dai, Longlong Wang, Xiangyu Dong, Yuan Gao, Lude Wei, Qixiong Zhang, Di Hu, Yifan Zhou:
Vertical Distribution of Water Vapor During Haze Processes in Northeast China Based on Raman Lidar Measurements. Remote. Sens. 16(19): 3713 (2024)- 2021
- [j5]Zheng Huang, Hongxing Wang, Tianpei Zhang, Yu Bin:
The Collaborative Power Inspection Task Allocation Method of "Unmanned Aerial Vehicle and Operating Vehicle". IEEE Access 9: 62926-62934 (2021)
2000 – 2009
- 2009
- [j4]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Substrate Topological Routing for High-Density Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(2): 207-216 (2009) - 2008
- [j3]Tianpei Zhang, Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design. Integr. 41(2): 171-182 (2008) - [c6]Shenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong:
Topological routing to maximize routability for package substrate. DAC 2008: 566-569 - 2007
- [j2]Tianpei Zhang, Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 624-636 (2007) - [c5]Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar:
Module assignment for pin-limited designs under the stacked-Vdd paradigm. ICCAD 2007: 656-659 - 2006
- [c4]Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar:
Temperature-aware routing in 3D ICs. ASP-DAC 2006: 309-314 - 2005
- [j1]Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar:
Placement and Routing in 3D Integrated Circuits. IEEE Des. Test Comput. 22(6): 520-531 (2005) - [c3]Tianpei Zhang, Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design. ASP-DAC 2005: 23-26 - 2004
- [c2]Tianpei Zhang, Sachin S. Sapatnekar:
Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing. ICCD 2004: 93-98 - 2002
- [c1]Tianpei Zhang, Sachin S. Sapatnekar:
Optimized pin assignment for lower routing congestion after floorplanning phase. SLIP 2002: 17-21
Coauthor Index
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