IEEE Design & Test of Computers, Volume 22

Volume 22, Number 1, January-February 2005

EIC Message

• 
  Rajesh K. Gupta:
  Global competitiveness, outsourcing, and education in the semiconductor industry. 5-6

Features

• 
  Kenneth D. Wagner:
  Keeping current with silicon and systems technology in the mid-90s. 7-9

Special Section: Perspectives on Outsourcing

• 
  Stephen H. Unger:
  Is engineering a viable profession in the US? 10-11
• 
  T. J. Rodgers:
  The truth about outsourcing. 12-13
• 
  Alberto L. Sangiovanni-Vincentelli:
  The importance of innovation in the economy of advanced countries. 14-16

Panel Summaries

• 
  R. Chandramouli:
  Infrastructure IP design for repair in nanometer technologies. 17

Features

• 
  Tiehan Lv, Jiang Xu, Wayne H. Wolf, I. Burak Özer, Jörg Henkel, Srimat T. Chakradhar:
  A Methodology for Architectural Design of Multimedia Multiprocessor SoCs. 18-26
• 
  Alberto La Rosa, Luciano Lavagno, Claudio Passerone:
  Software Development for High-Performance, Reconfigurable, Embedded Multimedia Systems. 28-38
• 
  Brian Delaney, Tajana Simunic, Nikil Jayant:
  Energy-Aware Distributed Speech Recognition for Wireless Mobile Devices. 39-49

Special Features

• 
  Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis:
  An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories. 50-58
• 
  Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra:
  Exploiting ECC Redundancy to Minimize Crosstalk Impact. 59-70

Standards

• 
  Victor Berman:
  Is it time to reexamine patent policy for standards? 71-73

Book Reviews

• 
  Sachin S. Sapatnekar:
  An EDA compendium. 74-75

Departments

• 
  Conference Reports. 76-78
• 
  DATC Newsletter. 79

The Last Byte

• 
  Scott Davidson:
  Testing: It's not just pass/fail anymore. 80

Volume 22, Number 2, March-April 2005

From the EIC

• 
  Rajesh K. Gupta:
  FPGA-enabled computing architectures. 81

Features

• 
  Patrick Lysaght, P. A. Subrahmanyam:
  Guest Editors' Introduction: Advances in Configurable Computing. 85-89
• 
  Bingfeng Mei, Andy Lambrechts, Diederik Verkest, Jean-Yves Mignolet, Rudy Lauwereins:
  Architecture Exploration for a Reconfigurable Architecture Template. 90-101
• 
  Miljan Vuletic, Laura Pozzi, Paolo Ienne:
  Seamless Hardware-Software Integration in Reconfigurable Computing Systems. 102-113
• 
  Chen Chang, John Wawrzynek, Robert W. Brodersen:
  BEE2: A High-End Reconfigurable Computing System. 114-125

Special Features

• 
  Daniel T. Hamling:
  Test Solution Selection Using Multiple-Objective Decision Models and Analyses. 126-134
• 
  Jürgen Becker, Alexander Thomas:
  Scalable Processor Instruction Set Extension. 136-148
• 
  Chulsung Park, Jinfeng Liu, Pai H. Chou:
  B#: A Battery Emulator and Power-Profiling Instrument. 150-159
• 
  Ming Shae Wu, Chung-Len Lee:
  Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults. 160-169
• 
  Ken Wagner, Patrick P. Gelsinger:
  Driving the $5 Billion Innovation Engine at Intel: An Interview with Patrick P. Gelsinger, Digital Enterprise Group Senior Vice President and General Manager, Intel. 170-180

Standards

• 
  Victor Berman:
  Sharing standards work with Japan. 182-183

Book Reviews

• 
  Grant Martin:
  The network is the chip. 184-185

Panel Summaries

• 
  Carol Stolicny:
  ITC 2004 panels: Part 1. 186-189

Newsletter

• 
  DATC Newsletter. 190

The Last Byte

• 
  Tom Kean:
  Déjà vu, all over again. 192

Volume 22, Number 3, May-June 2005

From the EIC

• 
  Rajesh K. Gupta:
  The other face of design for manufacturability. 193

DAC Watch

• 
  Andrew B. Kahng, Grant Martin:
  DAC Highlights. 197-199

The New Face of Design for Manufacturability

• 
  Juan Antonio Carballo, Yervant Zorian, Raul Camposano, Andrzej J. Strojwas, John Kibarian, Dennis Wassung, Alex Alexanian, Steve Wigley, Neil Kelly:
  Guest Editors' Introduction: DFM Drives Changes in Design Flow. 200-205
• 
  Alfred K. Wong:
  Some Thoughts on the IC Design-Manufacture Interface. 206-213
• 
  Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja:
  Yield-Driven, False-Path-Aware Clock Skew Scheduling. 214-222
• 
  Jay Jahangiri, David Abercrombie:
  Value-Added Defect Testing Techniques. 224-231
• 
  Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green:
  Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below. 232-239
• 
  Robert Madge:
  New test paradigms for yield and manufacturability. 240-246

Special Features

• 
  Maher N. Mneimneh, Karem A. Sakallah:
  Principles of Sequential-Equivalence Verification. 248-257
• 
  Robert Baumann:
  Soft Errors in Advanced Computer Systems. 258-266

Interview

• 
  The Future Depends on Innovation: An Interview with Irwin M. Jacobs, cofounder, chairman, and CEO of Qualcomm. 268-279

Book Reviews

• 
  Sachin S. Sapatnekar:
  Empowering the designer. 280-281

Conference Reports

• 
  Thomas W. Williams:
  TTTC recognizes test visionary's lifetime contribution. 282, 285

Standards

• 
  Victor Berman:
  IEEE P1647 and P1800: Two approaches to standardization and language design. 283-285

DATC Newsletter

• 
  Design Automation Technical Committee Newsletter. 286

The Last Byte

• 
  Gary Smith:
  Design for manufacturability comes of age. 288

Volume 22, Number 4, July-August 2005

From the EIC

• 
  Rajesh K. Gupta:
  Nanotechnology: Where science of the small meets math of the large. 289, 294

Special Announcement

• 
  Giovanni De Micheli, Al Dunlop:
  IEEE Council for Electronic Design Automation: A new beginning. 293-294

Features

• 
  R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi:
  Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. 295-297
• 
  Darshan D. Thaker, François Impens, Isaac L. Chuang, Rajeevan Amirtharajah, Frederic T. Chong:
  Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era. 298-305
• 
  André DeHon, Helia Naeimi:
  Seven Strategies for Tolerating Highly Defective Fabrication. 306-315
• 
  Chen He, Margarida F. Jacome, Gustavo de Veciana:
  A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies. 316-326
• 
  Jie Han, Jianbo Gao, Yan Qi, Pieter Jonker, José A. B. Fortes:
  Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics. 328-339

Special Features

• 
  Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra:
  New ECC for Crosstalk Impact Minimization. 340-348
• 
  Mark L. Chang, Scott Hauck:
  Précis: A Usercentric Word-Length Optimization Tool. 349-361
• 
  Chong Zhao, Sujit Dey, Xiaoliang Bai:
  Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits. 362-375
• 
  Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Anirudh Devgan:
  Modeling and Analysis of Parametric Yield under Power and Performance Constraints. 376-385

Book Reviews

• 
  Scott Davidson:
  BIST the hard way. 386-387

Panel Summaries

• 
  Luigi Carro:
  Adding value to design and test through education: What are the challenges? 388, 390

Conference Reports

• 
  Conference Reports. 389-390

DATC Newsletter

• 
  Design Automation Technical Committee Newsletter. 391

The Last Byte

• 
  Scott Davidson:
  What's the problem? 392

Volume 22, Number 5, September-October 2005

From the EIC

• 
  Rajesh K. Gupta:
  On-chip networks. 393

DAC Report

• 
  Grant Martin:
  Wireless, ESL, DFM, and Power on Stage at 42nd DAC. 397-398

Features

• 
  André Ivanov, Giovanni De Micheli:
  Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research. 399-403
• 
  Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli:
  Design, Synthesis, and Test of Networks on Chips. 404-413
• 
  Kees Goossens, John Dielissen, Andrei Radulescu:
  Æthereal Network on Chip: Concepts, Architectures, and Implementations. 414-421
• 
  Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo:
  Analysis and Implementation of Practical, Cost-Effective Networks on Chips. 422-433
• 
  Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli:
  Analysis of Error Recovery Schemes for Networks on Chips. 434-442
• 
  Christophe Bobda, Ali Ahmadinia:
  Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices. 443-451

Special Features

• 
  Javier Resano, Daniel Mozos, Diederik Verkest, Francky Catthoor:
  A Reconfiguration Manager for Dynamically Reconfigurable Hardware. 452-460
• 
  Braulio Adriano de Mello, Uilian Rafael Feijo Souza, Josué Klafke Sperb, Flávio Rech Wagner:
  Tangram: Virtual Integration of IP Components in a Distributed Cosimulation. 462-471

Interview

• 
  Inventions: A Result of Risk-Taking, Diversity, and Holistic Thinking - An interview with Bernard S. Meyerson, IBM Fellow, Vice President, and Chief Technologist of IBM's System Technology Group. 472-477

Book Reviews

• 
  Grant Martin:
  Verification by the pound. 478-479

Conference Reports

• 
  Conference Reports. 480-481

Panel Summaries

• 
  Panel Summaries. 482-483

Standards

• 
  Victor Berman:
  An update on IEEE P1647: The e system verification language. 484-486

DATC Newsletter

• 
  DATC Newsletter. 487

The Last Byte

• 
  Resve A. Saleh:
  An approach that will NoC your SoCs off! 488

Volume 22, Number 6, November-December 2005

From the EIC

• 
  Rajesh K. Gupta:
  Going 3D: Silicon and D&T. 493-494

Features

• 
  Sachin S. Sapatnekar, Kevin J. Nowka:
  Guest Editors' Introduction: New Dimensions in 3D Integration. 496-497
• 
  W. Rhett Davis, John M. Wilson, Stephen E. Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael B. Steer, Paul D. Franzon:
  Demystifying 3D ICs: The Pros and Cons of Going Vertical. 498-510
• 
  Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Jörg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher:
  3D Chip Stack Technology Using Through-Chip Interconnects. 512-518
• 
  Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar:
  Placement and Routing in 3D Integrated Circuits. 520-531
• 
  Sung Kyu Lim:
  Physical Design for 3D System on Package. 532-539
• 
  Philip Jacob, Okan Erdogan, Aamir Zia, Paul M. Belemjian, Russell P. Kraft, John F. McDonald:
  Predicting the Performance of a 3D Processor-Memory Chip Stack. 540-547
• 
  Annie (Yujuan) Zeng, James (JianQiang) Lü, Kenneth Rose, Ronald J. Gutmann:
  First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration. 548-555
• 
  Christianto C. Liu, Ilya Ganusov, Martin Burtscher, Sandip Tiwari:
  Bridging the Processor-Memory Performance Gapwith 3D IC Technology. 556-564

Special ITC Section

• 
  Scott Davidson:
  Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive. 565
• 
  Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher, Nishant Patil:
  X-Tolerant Test Response Compaction. 566-574
• 
  Xiao Liu, Michael S. Hsiao:
  A Novel Transition Fault ATPG That Reduces Yield Loss. 576-584
• 
  Sagar S. Sabade, Duncan M. Hank Walker:
  IC Outlier Identification Using Multiple Test Metrics. 586-595

Book Reviews

• 
  Sachin S. Sapatnekar:
  Designing "Vary" Good Circuitry. 596-597

Panel Summaries

• 
  Panel Summaries. 598-599

Conference Reports

• 
  Vladimir Hahanov:
  2005 IEEE East-West Design and Test Workshop. 600

TTTC Newsletter

• 
  Test Technology TC Newsletter. 602-603

The Last Byte

• 
  Robert C. Aitken:
  ITC is Cool. 616