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2000 – 2009
- 2007
[c5]Brent Goplen, Sachin S. Sapatnekar:
Placement of 3D ICs with Thermal and Interlayer Via Considerations. DAC 2007: 626-631- 2006
- [j3]Jeng-Liang Tsai, Charlie Chung-Ping Chen, Guoqiang Chen, Brent Goplen, Haifeng Qian
, Yong Zhan, Sung-Mo Kang, Martin D. F. Wong, Sachin S. Sapatnekar:
Temperature-Aware Placement for SOCs. Proc. IEEE 94(8): 1502-1518 (2006) - [j2]Brent Goplen, Sachin S. Sapatnekar:
Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 692-709 (2006) - [c4]Yong Zhan, Brent Goplen, Sachin S. Sapatnekar:
Electrothermal analysis and optimization techniques for nanoscale integrated circuits. ASP-DAC 2006: 219-222 - 2005
- [j1]Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar:
Placement and Routing in 3D Integrated Circuits. IEEE Des. Test Comput. 22(6): 520-531 (2005) - [c3]Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar:
Net weighting to reduce repeater counts during placement. DAC 2005: 503-508 - [c2]Brent Goplen, Sachin S. Sapatnekar:
Thermal via placement in 3D ICs. ISPD 2005: 167-174 - 2003
- [c1]Brent Goplen, Sachin S. Sapatnekar:
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach. ICCAD 2003: 86-90
Coauthor Index
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