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2000 – 2009
- 2009
[j8]Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Se-Joong Lee, Hoi-Jun Yoo:
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 370-383 (2009)- 2006
- [j7]Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
Low-power network-on-chip for high-performance SoC design. IEEE Trans. Very Large Scale Integr. Syst. 14(2): 148-160 (2006) - [c12]Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho, Hoi-Jun Yoo:
A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes. DATE 2006: 79-80 - 2005
- [j6]Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo:
Analysis and Implementation of Practical, Cost-Effective Networks on Chips. IEEE Des. Test Comput. 22(5): 422-433 (2005) - [j5]Se-Joong Lee, Kangmin Lee, Seong-Jun Song, Hoi-Jun Yoo:
Packet-switched on-chip interconnection network for system-on-chip applications. IEEE Trans. Circuits Syst. II Express Briefs 52-II(6): 308-312 (2005) - [c11]Kwanho Kim, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo:
An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip. ISCAS (3) 2005: 2357-2360 - [c10]Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. ISCAS (3) 2005: 2369-2372 - 2004
- [c9]Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
SILENT: serialized low energy transmission coding for on-chip interconnection networks. ICCAD 2004: 448-451 - [c8]Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
Low energy transmission coding for on-chip serial communications. SoCC 2004: 177-178 - [c7]Jong-Sun Kim, Min-Su Hwang, Seungsu Roh, Ja-Young Lee, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
On-chip network based embedded core testing. SoCC 2004: 223-226 - 2003
- [c6]Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
A distributed crossbar switch scheduler for on-chip networks. CICC 2003: 671-674 - [c5]Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks. ESSCIRC 2003: 453-456 - [c4]Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output buffer. ESSCIRC 2003: 461-464 - 2002
- [j4]Se-Joong Lee, Hoi-Jun Yoo:
Race logic architecture (RALA): a novel logic concept using the race scheme of input variables. IEEE J. Solid State Circuits 37(2): 191-201 (2002) - [j3]Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo:
A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. IEEE J. Solid State Circuits 37(5): 612-623 (2002) - [j2]Ramchan Woo, Chi Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Hoi-Jun Yoo:
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip. IEEE J. Solid State Circuits 37(10): 1352-1355 (2002) - [c3]Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo:
A practical method to use eDRAM in the shared bus packet switch. GLOBECOM 2002: 2303-2307 - 2001
- [j1]Chi Weon Yoon, Ramchan Woo, Jeengheon Kook, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yeo:
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications. IEEE J. Solid State Circuits 36(11): 1758-1767 (2001) - 2000
- [c2]Se-Joong Lee, Jinho Han, Seung-Ho Hank, Joe-Ho Lee, Jung-Su Kim, Minkyu Je, Hoi-Jun Yoo:
One chip-low power digital-TCXO with sub-ppm accuracy. ISCAS 2000: 17-20 - [c1]Ramchan Woo, Se-Joong Lee, Hoi-Jun Yoo:
A 670 ps, 64 bit dynamic low-power adder design. ISCAS 2000: 28-31
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