"Buffering global interconnects in structured ASIC design."

Tianpei Zhang, Sachin S. Sapatnekar (2008)

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DOI: 10.1016/J.VLSI.2007.04.002

access: closed

type: Journal Article

metadata version: 2020-02-20

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Tianpei Zhang, Sachin S. Sapatnekar:
Buffering global interconnects in structured ASIC design. Integr. 41(2): 171-182 (2008)

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