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ORCIDACM Journal on Emerging Technologies in Computing Systems, Volume 13
Volume 13, Number 1, June 2016
- Ozgur Sinanoglu
, Ramesh Karri:
Guest Editorial Special Issue on Secure and Trustworthy Computing. 1:1-1:3 - Jayita Das, Kevin Scott, Sanjukta Bhanja:
MRAM PUF: Using Geometric and Resistive Variations in MRAM Cells. 2:1-2:15 - Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Xunzhao Yin, Xiaobo Sharon Hu, Michael T. Niemier, Yier Jin:
Emerging Technology-Based Design of Primitives for Hardware Security. 3:1-3:19 - Anirudh Iyengar, Swaroop Ghosh, Kenneth Ramclam, Jae-Won Jang, Cheng-Wei Lin:
Spintronic PUFs for Security, Trust, and Authentication. 4:1-4:15 - Elena Ioana Vatajelu, Giorgio Di Natale, Mario Barbareschi, Lionel Torres, Marco Indaco, Paolo Prinetto:
STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability. 5:1-5:21 - Shahed E. Quadir, Junlin Chen, Domenic Forte, Navid Asadizanjani, Sina Shahbazmohamadi, Lei Wang, John A. Chandy, Mark M. Tehranipoor:
A Survey on Chip to System Reverse Engineering. 6:1-6:34 - Stephan De Castro, Jean-Max Dutertre, Bruno Rouzeyre, Giorgio Di Natale, Marie-Lise Flottes:
Frontside Versus Backside Laser Injection: A Comparative Study. 6:1-6:15 - Alessandro Barenghi, Guido Marco Bertoni, Luca Breveglieri, Gerardo Pelosi, Stefano Sanfilippo, Ruggero Susella:
A Fault-Based Secret Key Retrieval Method for ECDSA: Analysis and Countermeasure. 8:1-8:26 - Yingjie Lao, Qianying Tang, Chris H. Kim, Keshab K. Parhi:
Beat Frequency Detector-Based High-Speed True Random Number Generators: Statistical Modeling and Analysis. 9:1-9:25 - Amey M. Kulkarni, Youngok K. Pino, Matthew French, Tinoosh Mohsenin:
Real-Time Anomaly Detection Framework for Many-Core Router through Machine-Learning Techniques. 10:1-10:22 - Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler:
Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits. 11:1-11:13
Volume 13, Number 2, November 2016
- Aida Todri-Sanial, Saraju P. Mohanty, Mariane Comte, Marc Belleville:
Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era. 12:1-12:2 - Yan Fang, Victor V. Yashin, Brandon B. Jennings, Donald M. Chiarulli, Steven P. Levitan:
A Simplified Phase Model for Simulation of Oscillator-Based Computing Systems. 14:1-14:20 - Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney Laert Vilar Calazans, Peter A. Beerel:
A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits. 15:1-15:23 - Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda:
A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. 16:1-16:13 - Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatié:
Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices. 17:1-17:23
- Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy:
Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC. 20:1-20:20 - Meghna G. Mankalale, Sachin S. Sapatnekar:
Optimized Standard Cells for All-Spin Logic. 21:1-21:22 - Wei Jiang, Liang Wen, Ke Jiang, Xia Zhang, Xiong Pan, Keran Zhou:
System-Level Design to Detect Fault Injection Attacks on Embedded Real-Time Applications. 22:1-22:18 - A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy:
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes. 23:1-23:22 - José L. Abellán, Chao Chen, Ajay Joshi:
Electro-Photonic NoC Designs for Kilocore Systems. 24:1-24:25 - Abdullah Guler, Niraj K. Jha:
Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs. 26:1-26:25 - Hang Zhang, Xuhao Chen, Nong Xiao, Lei Wang, Fang Liu, Wei Chen, Zhiguang Chen:
Shielding STT-RAM Based Register Files on GPUs against Read Disturbance. 27:1-27:17 - Arnab Kumar Biswas:
Source Authentication Techniques for Network-on-Chip Router Configuration Packets. 28:1-28:31 - Sparsh Mittal:
A Survey of Techniques for Architecting Processor Components Using Domain-Wall Memory. 29:1-29:25 - Anderson L. Sartor, Arthur Francisco Lorenzon, Luigi Carro, Fernanda Lima Kastensmidt, Stephan Wong, Antonio C. S. Beck:
Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors. 13:1-13:21 - Joydeep Rakshit, Kartik Mohanram, Runlai Wan, Kai Tak Lam, Jing Guo:
Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems. 18:1-18:28 - Xuan Wang, Jiang Xu, Zhe Wang, Haoran Li, Peng Yang, Luan H. K. Duong, Rafael K. V. Maeda, Zhifei Wang:
Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign. 19:1-19:24 - Yao Wang, Liang Rong, Haibo Wang, Guangjun Wen:
One-Step Sneak-Path Free Read Scheme for Resistive Crossbar Memory. 25:1-25:18
Volume 13, Number 3, May 2017
Special Issue on Hardware and Algorithms for Learning On-a-chip
- Yu Cao, Xin Li, Taemin Kim, Suyog Gupta:
Guest Editors' Introduction: Hardware and Algorithms for On-Chip Learning. 30:1-30:3 - Adam Page, Ali Jafari, Colin Shea, Tinoosh Mohsenin:
SPARCNet: A Hardware Accelerator for Efficient Deployment of Sparse Convolutional Networks. 31:1-31:32 - Sajid Anwar, Kyuyeon Hwang, Wonyong Sung:
Structured Pruning of Deep Convolutional Neural Networks. 32:1-32:18 - Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy:
Energy-Efficient and Improved Image Recognition with Conditional Deep Learning. 33:1-33:21 - Robert Karam, Somnath Paul, Ruchir Puri, Swarup Bhunia:
Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications. 34:1-34:24 - Bo Yuan, Keshab K. Parhi:
VLSI Architectures for the Restricted Boltzmann Machine. 35:1-35:19 - Leibin Ni, Hantao Huang, Zichuan Liu, Rajiv V. Joshi, Hao Yu:
Distributed In-Memory Computing on Binary RRAM Crossbar. 36:1-36:18 - Cory E. Merkel, Dhireesha Kudithipudi, Manan Suri, Bryant T. Wysocki:
Stochastic CBRAM-Based Neuromorphic Time Series Prediction System. 37:1-37:14
- Rasit Onur Topaloglu, Naveen Verma:
Editorial for JETC Special Issue on Alternative Computing Systems. 38:1-38:2 - Keith A. Britt, Travis S. Humble:
High-Performance Computing with Quantum Processing Units. 39:1-39:13 - Su-Kyung Yoon, Young-Sun Youn, Kihyun Park, Shin-Dug Kim:
Mobile Unified Memory-Storage Structure Based on Hybrid Non-Volatile Memories. 40:1-40:18 - Krishnendu Guha, Debasri Saha, Amlan Chakrabarti:
Real-Time SoC Security against Passive Threats Using Crypsis Behavior of Geckos. 41:1-41:26 - Yin Liu, Keshab K. Parhi:
Computing Polynomials Using Unipolar Stochastic Logic. 42:1-42:30 - Pareesa Ameneh Golnari, Yavuz Yetim, Margaret Martonosi, Yakir Vizel, Sharad Malik:
PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees. 43:1-43:29 - Anusha Gorantla, Deepa P:
Design of Approximate Compressors for Multiplication. 44:1-44:17 - Arvind Kumar, Zhe Wan, Winfried W. Wilcke, Subramanian S. Iyer:
Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration. 45:1-45:21 - Mohammed Alawad, Mingjie Lin:
Sketching Computation with Stochastic Processing Engines. 46:1-46:19 - Armin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li:
Trading Accuracy for Energy in Stochastic Circuit Design. 47:1-47:30 - Soheil Salehi, Deliang Fan, Ronald F. DeMara:
Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency. 48:1-48:16 - Songping Yu, Nong Xiao, Mingzhu Deng, Fang Liu, Wei Chen:
Redesign the Memory Allocator for Non-Volatile Main Memory. 49:1-49:26 - Bing Li, Yu Hu, Ying Wang, Jing Ye, Xiaowei Li:
Power-Utility-Driven Write Management for MLC PCM. 50:1-50:22
Volume 13, Number 4, August 2017
- Mrityunjay Ghosh, Amlan Chakrabarti, Niraj K. Jha:
Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle. 51:1-51:14 - Rekha Govindaraj, Swaroop Ghosh:
Design and Analysis of STTRAM-Based Ternary Content Addressable Memory Cell. 52:1-52:22 - Eldhose Peter, Anuj Arora, Janibul Bashir, Akriti Bagaria, Smruti R. Sarangi:
Optical Overlay NUCA: A High-Speed Substrate for Shared L2 Caches. 53:1-53:25 - Abhishek Koneru, Sukeshwar Kannan, Krishnendu Chakrabarty:
Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits. 54:1-54:23 - Mahboobeh Houshmand, Mehdi Sedighi, Morteza Saheb Zamani, Kourosh Marjoei:
Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics. 55:1-55:27 - Karthik Yogendra, Chamika M. Liyanagedera, Deliang Fan, Yong Shim, Kaushik Roy:
Coupled Spin-Torque Nano-Oscillator-Based Computation: A Simulation Study. 56:1-56:24 - M. Hassan Najafi, Peng Li, David J. Lilja, Weikang Qian, Kia Bazargan, Marc D. Riedel:
A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing. 57:1-57:28 - Sai Vineel Reddy Chittamuru, Srinivas Desai, Sudeep Pasricha:
SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast-Enabled Channel Sharing for Multicore Architectures. 58:1-58:27 - Sandeep Kumar Samal, Guoqing Chen, Sung Kyu Lim:
Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs. 59:1-59:18 - Honglan Jiang, Cong Liu, Leibo Liu, Fabrizio Lombardi, Jie Han:
A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits. 60:1-60:34 - Hui Li, Sébastien Le Beux, Martha Johanna Sepúlveda, Ian O'Connor:
Energy-Efficiency Comparison of Multi-Layer Deposited Nanophotonic Crossbar Interconnects. 61:1-61:25
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