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ORCIDNiraj K. Jha
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- affiliation: Princeton University, USA
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2020 – today
- 2024
[j235]Chang Yue
, Niraj K. Jha:
CTRL: Clustering Training Losses for Label Error Detection. IEEE Trans. Artif. Intell. 5(8): 4121-4135 (2024)- [j234]Chia-Hao Li, Niraj K. Jha:
DOCTOR: A Multi-Disease Detection Continual Learning Framework Based on Wearable Medical Sensors. ACM Trans. Embed. Comput. Syst. 23(5): 81:1-81:33 (2024) - [j233]Shikhar Tuli, Niraj K. Jha:
EdgeTran: Device-Aware Co-Search of Transformers for Efficient Inference on Mobile Edge Platforms. IEEE Trans. Mob. Comput. 23(6): 7012-7029 (2024) - [c213]Hongjie Wang, Bhishma Dedhia, Niraj K. Jha:
Zero-TPrune: Zero-Shot Token Pruning Through Leveraging of the Attention Graph in Pre-Trained Transformers. CVPR 2024: 16070-16079 - [c212]Hongjie Wang, Difan Liu, Yan Kang, Yijun Li, Zhe Lin, Niraj K. Jha, Yuchen Liu:
Attention-Driven Training-Free Efficiency Enhancement of Diffusion Models. CVPR 2024: 16080-16089 - [c211]Shikhar Tuli, Chi-Heng Lin, Yen-Chang Hsu, Niraj K. Jha, Yilin Shen, Hongxia Jin:
DynaMo: Accelerating Language Model Inference with Dynamic Multi-Token Sampling. NAACL-HLT 2024: 3322-3345 - [i48]Bhishma Dedhia, Niraj K. Jha:
Neural Slot Interpreters: Grounding Object Semantics in Emergent Slot Representations. CoRR abs/2403.07887 (2024) - [i47]Chia-Hao Li, Niraj K. Jha:
PAGE: Domain-Incremental Adaptation with Past-Agnostic Generative Replay for Smart Healthcare. CoRR abs/2403.08197 (2024) - [i46]Shikhar Tuli, Chi-Heng Lin, Yen-Chang Hsu, Niraj K. Jha, Yilin Shen, Hongxia Jin:
DynaMo: Accelerating Language Model Inference with Dynamic Multi-Token Sampling. CoRR abs/2405.00888 (2024) - [i45]Hongjie Wang, Difan Liu, Yan Kang, Yijun Li, Zhe Lin, Niraj K. Jha, Yuchen Liu:
Attention-Driven Training-Free Efficiency Enhancement of Diffusion Models. CoRR abs/2405.05252 (2024) - [i44]Linhui Huang, Sayeri Lala, Niraj K. Jha:
CONFINE: Conformal Prediction for Interpretable Neural Networks. CoRR abs/2406.00539 (2024) - [i43]Sayeri Lala, Niraj K. Jha:
METRIK: Measurement-Efficient Randomized Controlled Trials using Transformers with Input Masking. CoRR abs/2406.16351 (2024) - [i42]Chang Yue, Niraj K. Jha:
Learning Interpretable Differentiable Logic Networks. CoRR abs/2407.04168 (2024) - [i41]Chia-Hao Li, Niraj K. Jha:
COMFORT: A Continual Fine-Tuning Framework for Foundation Models Targeted at Consumer Healthcare. CoRR abs/2409.09549 (2024) - [i40]Hongjie Wang, Chih-Yao Ma, Yen-Cheng Liu, Ji Hou, Tao Xu, Jialiang Wang, Felix Juefei-Xu, Yaqiao Luo, Peizhao Zhang, Tingbo Hou, Peter Vajda, Niraj K. Jha, Xiaoliang Dai:
LinGen: Towards High-Resolution Minute-Length Text-to-Video Generation with Linear Computational Complexity. CoRR abs/2412.09856 (2024) - 2023
- [j232]Bhishma Dedhia, Roshini Balasubramanian, Niraj K. Jha:
SCouT: Synthetic Counterfactuals via Spatiotemporal Transformers for Actionable Healthcare. ACM Trans. Comput. Heal. 4(4): 23:1-23:28 (2023) - [j231]Shikhar Tuli, Bhishma Dedhia, Shreshth Tuli, Niraj K. Jha:
FlexiBERT: Are Current Transformer Architectures too Homogeneous and Rigid? J. Artif. Intell. Res. 77: 39-70 (2023) - [j230]Shayan Hassantabar, Prerit Terway, Niraj K. Jha:
TUTOR: Training Neural Networks Using Decision Rules as Model Priors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 483-496 (2023) - [j229]Prerit Terway, Niraj K. Jha:
INFORM: Inverse Design Methodology for Constrained Multiobjective Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2200-2213 (2023) - [j228]Shikhar Tuli, Niraj K. Jha:
AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference With Transformers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4038-4051 (2023) - [j227]Shikhar Tuli, Niraj K. Jha:
TransCODE: Co-Design of Transformers and Accelerators for Efficient Training and Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4817-4830 (2023) - [j226]Shikhar Tuli, Chia-Hao Li, Ritvik Sharma, Niraj K. Jha:
CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. ACM Trans. Embed. Comput. Syst. 22(3): 51:1-51:30 (2023) - [j225]Prerit Terway, Niraj K. Jha:
REPAIRS: Gaussian Mixture Model-based Completion and Optimization of Partially Specified Systems. ACM Trans. Embed. Comput. Syst. 22(4): 69:1-69:36 (2023) - [c210]Sanjai Narain, Dana Chee, Pranav Iyer, Emily Mak, Ricardo Valdez, Manli Zhu, Niraj K. Jha, Jaime F. Fisac, Kai-Chieh Hsu, Prerit Terway, Kishore Pochiraju, Brendan J. Englot, Emil Pitz, Sean Rooney, Yewei Huang:
AIMED: AI-Mediated Exploration of Design: An Experience Report. CPS-IoT Week Workshops 2023: 136-140 - [c209]Niraj K. Jha:
Smart Healthcare. ACM Great Lakes Symposium on VLSI 2023: 1 - [c208]Bhishma Dedhia, Michael Chang, Jake Snell, Tom Griffiths, Niraj K. Jha:
Im-Promptu: In-Context Composition from Image Prompts. NeurIPS 2023 - [i39]Tanujay Saha, Tamjid Al Rahat, Najwa Aaraj, Yuan Tian, Niraj K. Jha:
ML-FEED: Machine Learning Framework for Efficient Exploit Detection (Extended version). CoRR abs/2301.04314 (2023) - [i38]Shikhar Tuli, Niraj K. Jha:
AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference with Transformers. CoRR abs/2302.14705 (2023) - [i37]Shikhar Tuli, Niraj K. Jha:
EdgeTran: Co-designing Transformers for Efficient Inference on Mobile Edge Platforms. CoRR abs/2303.13745 (2023) - [i36]Shikhar Tuli, Niraj K. Jha:
TransCODE: Co-design of Transformers and Accelerators for Efficient Training and Inference. CoRR abs/2303.14882 (2023) - [i35]Sayeri Lala, Niraj K. Jha:
SECRETS: Subject-Efficient Clinical Randomized Controlled Trials using Synthetic Intervention. CoRR abs/2305.05078 (2023) - [i34]Chia-Hao Li, Niraj K. Jha:
DOCTOR: A Multi-Disease Detection Continual Learning Framework Based on Wearable Medical Sensors. CoRR abs/2305.05738 (2023) - [i33]Bhishma Dedhia, Michael Chang, Jake C. Snell, Thomas L. Griffiths, Niraj K. Jha:
Im-Promptu: In-Context Composition from Image Prompts. CoRR abs/2305.17262 (2023) - [i32]Hongjie Wang, Bhishma Dedhia, Niraj K. Jha:
Zero-TPrune: Zero-Shot Token Pruning through Leveraging of the Attention Graph in Pre-Trained Transformers. CoRR abs/2305.17328 (2023) - [i31]Shikhar Tuli, Niraj K. Jha:
BREATHE: Second-Order Gradients and Heteroscedastic Emulation based Design Space Exploration. CoRR abs/2308.08666 (2023) - 2022
- [j224]Sanjai Narain, Emily Mak, Dana Chee, Brendan J. Englot, Kishore Pochiraju, Niraj K. Jha, Karthik S. Narayan:
Fast Design Space Exploration of Nonlinear Systems: Part I. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2970-2983 (2022) - [j223]Prerit Terway, Kenza Hamidouche, Niraj K. Jha:
Fast Design Space Exploration of Nonlinear Systems: Part II. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 2984-2999 (2022) - [j222]Shayan Hassantabar, Zeyu Wang, Niraj K. Jha:
SCANN: Synthesis of Compact and Accurate Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3012-3025 (2022) - [j221]Shayan Hassantabar, Xiaoliang Dai, Niraj K. Jha:
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4975-4990 (2022) - [j220]Shayan Hassantabar, Joe Zhang, Hongxu Yin, Niraj K. Jha:
MHDeep: Mental Health Disorder Detection System Based on Wearable Sensors and Artificial Neural Networks. ACM Trans. Embed. Comput. Syst. 21(6): 81:1-81:22 (2022) - [j219]Ye Yu, Niraj K. Jha:
SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference. IEEE Trans. Emerg. Top. Comput. 10(1): 237-249 (2022) - [j218]Xiaoliang Dai, Hongxu Yin, Niraj K. Jha:
Incremental Learning Using a Grow-and-Prune Paradigm With Efficient Neural Networks. IEEE Trans. Emerg. Top. Comput. 10(2): 752-762 (2022) - [j217]Tanujay Saha, Najwa Aaraj, Neel Ajjarapu, Niraj K. Jha:
SHARKS: Smart Hacking Approaches for RisK Scanning in Internet-of-Things and Cyber-Physical Systems Based on Machine Learning. IEEE Trans. Emerg. Top. Comput. 10(2): 870-885 (2022) - [j216]Wenhan Xia, Hongxu Yin, Xiaoliang Dai, Niraj K. Jha:
Fully Dynamic Inference With Deep Neural Networks. IEEE Trans. Emerg. Top. Comput. 10(2): 962-972 (2022) - [j215]Jie Lu, Naveen Verma, Niraj K. Jha:
Convolutional Autoencoder-Based Transfer Learning for Multi-Task Image Inferences. IEEE Trans. Emerg. Top. Comput. 10(2): 1045-1057 (2022) - [j214]Jacob Brown, Tanujay Saha, Niraj K. Jha:
GRAVITAS: Graphical Reticulated Attack Vectors for Internet-of-Things Aggregate Security. IEEE Trans. Emerg. Top. Comput. 10(3): 1331-1348 (2022) - [j213]Hongxu Yin, Guoyang Chen, Yingmin Li, Shuai Che, Weifeng Zhang, Niraj K. Jha:
Towards Execution-Efficient LSTMs via Hardware-Guided Grow-and-Prune Paradigm. IEEE Trans. Emerg. Top. Comput. 10(4): 1799-1809 (2022) - [j212]Tanujay Saha, Najwa Aaraj, Niraj K. Jha:
Machine Learning Assisted Security Analysis of 5G-Network-Connected Systems. IEEE Trans. Emerg. Top. Comput. 10(4): 2006-2024 (2022) - [c207]Tanujay Saha, Tamjid Al Rahat, Najwa Aaraj, Yuan Tian, Niraj K. Jha:
ML-FEED: Machine Learning Framework for Efficient Exploit Detection. TPS-ISA 2022: 140-149 - [i30]Shikhar Tuli, Bhishma Dedhia, Shreshth Tuli, Niraj K. Jha:
FlexiBERT: Are Current Transformer Architectures too Homogeneous and Rigid? CoRR abs/2205.11656 (2022) - [i29]Bhishma Dedhia, Roshini Balasubramanian, Niraj K. Jha:
SCouT: Synthetic Counterfactuals via Spatiotemporal Transformers for Actionable Healthcare. CoRR abs/2207.04208 (2022) - [i28]Chang Yue, Niraj K. Jha:
CTRL: Clustering Training Losses for Label Error Detection. CoRR abs/2208.08464 (2022) - [i27]Shikhar Tuli, Chia-Hao Li, Ritvik Sharma, Niraj K. Jha:
CODEBench: A Neural Architecture and Hardware Accelerator Co-Design Framework. CoRR abs/2212.03965 (2022) - 2021
- [j211]Ye Yu, Yingmin Li, Shuai Che, Niraj K. Jha, Weifeng Zhang:
Software-Defined Design Space Exploration for an Efficient DNN Accelerator Architecture. IEEE Trans. Computers 70(1): 45-56 (2021) - [j210]Ayten Ozge Akmandor, Jorge Ortiz, Irene Manotas, Bongjun Ko, Niraj K. Jha:
SECRET: Semantically Enhanced Classification of Real-World Tasks. IEEE Trans. Computers 70(3): 440-456 (2021) - [j209]Shayan Hassantabar, Novati Stefano, Vishweshwar Ghanakota, Alessandra Ferrari, Gregory N. Nicola, Raffaele Bruno, Ignazio R. Marino, Kenza Hamidouche, Niraj K. Jha:
CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks. IEEE Trans. Consumer Electron. 67(4): 244-256 (2021) - [j208]Hongxu Yin, Bilal Mukadam, Xiaoliang Dai, Niraj K. Jha:
DiabDeep: Pervasive Diabetes Diagnosis Based on Wearable Medical Sensors and Efficient Neural Networks. IEEE Trans. Emerg. Top. Comput. 9(3): 1139-1150 (2021) - [j207]Ayten Ozge Akmandor, Xiaoliang Dai, Niraj K. Jha:
YSUY: Your Smartphone Understands You - Using Machine Learning to Address Fundamental Human Needs. IEEE Trans. Syst. Man Cybern. Syst. 51(12): 7553-7568 (2021) - [i26]Tanujay Saha, Najwa Aaraj, Neel Ajjarapu, Niraj K. Jha:
SHARKS: Smart Hacking Approaches for RisK Scanning in Internet-of-Things and Cyber-Physical Systems based on Machine Learning. CoRR abs/2101.02780 (2021) - [i25]Shayan Hassantabar, Joe Zhang, Hongxu Yin, Niraj K. Jha:
MHDeep: Mental Health Disorder Detection System based on Body-Area and Deep Neural Networks. CoRR abs/2102.10435 (2021) - [i24]Malin Prematilake, Younghyun Kim, Vijay Raghunathan, Anand Raghunathan, Niraj K. Jha:
HW/SW Framework for Improving the Safety of Implantable and Wearable Medical Devices. CoRR abs/2103.01781 (2021) - [i23]Sanjai Narain, Emily Mak, Dana Chee, Brendan J. Englot, Kishore Pochiraju, Niraj K. Jha, Karthik S. Narayan:
Fast Design Space Exploration of Nonlinear Systems: Part I. CoRR abs/2104.01747 (2021) - [i22]Prerit Terway, Kenza Hamidouche, Niraj K. Jha:
Fast Design Space Exploration of Nonlinear Systems: Part II. CoRR abs/2104.02464 (2021) - [i21]Jacob Brown, Tanujay Saha, Niraj K. Jha:
GRAVITAS: Graphical Reticulated Attack Vectors for Internet-of-Things Aggregate Security. CoRR abs/2106.00073 (2021) - [i20]Tanujay Saha, Najwa Aaraj, Niraj K. Jha:
Machine Learning Assisted Security Analysis of 5G-Network-Connected Systems. CoRR abs/2108.03514 (2021) - 2020
- [j206]Xiaoliang Dai, Hongxu Yin, Niraj K. Jha:
Grow and Prune Compact, Fast, and Accurate LSTMs. IEEE Trans. Computers 69(3): 441-452 (2020) - [j205]Abdullah Guler, Niraj K. Jha:
McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems. IEEE Trans. Very Large Scale Integr. Syst. 28(10): 2146-2156 (2020) - [c206]Hongxu Yin, Pavlo Molchanov, José M. Álvarez, Zhizhong Li, Arun Mallya, Derek Hoiem, Niraj K. Jha, Jan Kautz:
Dreaming to Distill: Data-Free Knowledge Transfer via DeepInversion. CVPR 2020: 8712-8721 - [c205]Wenhan Xia, Hongxu Yin, Niraj K. Jha:
INVITED: Efficient Synthesis of Compact Deep Neural Networks. DAC 2020: 1-6 - [i19]Wenhan Xia, Hongxu Yin, Niraj K. Jha:
Efficient Synthesis of Compact Deep Neural Networks. CoRR abs/2004.08704 (2020) - [i18]Shayan Hassantabar, Novati Stefano, Vishweshwar Ghanakota, Alessandra Ferrari, Gregory N. Nicola, Raffaele Bruno, Ignazio R. Marino, Niraj K. Jha:
CovidDeep: SARS-CoV-2/COVID-19 Test Based on Wearable Medical Sensors and Efficient Neural Networks. CoRR abs/2007.10497 (2020) - [i17]Wenhan Xia, Hongxu Yin, Xiaoliang Dai, Niraj K. Jha:
Fully Dynamic Inference with Deep Neural Networks. CoRR abs/2007.15151 (2020) - [i16]Prerit Terway, Kenza Hamidouche, Niraj K. Jha:
DISPATCH: Design Space Exploration of Cyber-Physical Systems. CoRR abs/2009.10214 (2020) - [i15]Shayan Hassantabar, Prerit Terway, Niraj K. Jha:
TUTOR: Training Neural Networks Using Decision Rules as Model Priors. CoRR abs/2010.05429 (2020) - [i14]Sanjai Narain, Emily Mak, Dana Chee, Todd Huster, Jeremy E. J. Cohen, Kishore Pochiraju, Brendan J. Englot, Niraj K. Jha, Karthik S. Narayan:
Robot Design With Neural Networks, MILP Solvers and Active Learning. CoRR abs/2010.09842 (2020)
2010 – 2019
- 2019
- [j204]Xiaoliang Dai, Hongxu Yin, Niraj K. Jha:
NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm. IEEE Trans. Computers 68(10): 1487-1497 (2019) - [j203]Abdullah Guler, Niraj K. Jha:
Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 899-912 (2019) - [c204]Xiaoliang Dai, Peizhao Zhang, Bichen Wu, Hongxu Yin, Fei Sun, Yanghan Wang, Marat Dukhan, Yunqing Hu, Yiming Wu, Yangqing Jia, Peter Vajda, Matt Uyttendaele, Niraj K. Jha:
ChamNet: Towards Efficient Network Design Through Platform-Aware Model Adaptation. CVPR 2019: 11398-11407 - [i13]Hongxu Yin, Guoyang Chen, Yingmin Li, Shuai Che, Weifeng Zhang, Niraj K. Jha:
Hardware-Guided Symbiotic Training for Compact, Accurate, yet Execution-Efficient LSTM. CoRR abs/1901.10997 (2019) - [i12]Ye Yu, Yingmin Li, Shuai Che, Niraj K. Jha, Weifeng Zhang:
Software-Defined Design Space Exploration for an Efficient AI Accelerator Architecture. CoRR abs/1903.07676 (2019) - [i11]Shayan Hassantabar, Zeyu Wang, Niraj K. Jha:
SCANN: Synthesis of Compact and Accurate Neural Networks. CoRR abs/1904.09090 (2019) - [i10]Xiaoliang Dai, Hongxu Yin, Niraj K. Jha:
Incremental Learning Using a Grow-and-Prune Paradigm with Efficient Neural Networks. CoRR abs/1905.10952 (2019) - [i9]Ayten Ozge Akmandor, Jorge Ortiz, Irene Manotas, Bongjun Ko, Niraj K. Jha:
SECRET: Semantically Enhanced Classification of Real-world Tasks. CoRR abs/1905.12356 (2019) - [i8]Ye Yu, Niraj K. Jha:
SPRING: A Sparsity-Aware Reduced-Precision Monolithic 3D CNN Accelerator Architecture for Training and Inference. CoRR abs/1909.00557 (2019) - [i7]Hongxu Yin, Bilal Mukadam, Xiaoliang Dai, Niraj K. Jha:
DiabDeep: Pervasive Diabetes Diagnosis based on Wearable Medical Sensors and Efficient Neural Networks. CoRR abs/1910.04925 (2019) - [i6]Shayan Hassantabar, Xiaoliang Dai, Niraj K. Jha:
STEERAGE: Synthesis of Neural Networks Using Architecture Search and Grow-and-Prune Methods. CoRR abs/1912.05831 (2019) - [i5]Hongxu Yin, Pavlo Molchanov, Zhizhong Li, José M. Álvarez, Arun Mallya, Derek Hoiem, Niraj K. Jha, Jan Kautz:
Dreaming to Distill: Data-free Knowledge Transfer via DeepInversion. CoRR abs/1912.08795 (2019) - 2018
- [j202]Ayten Ozge Akmandor, Niraj K. Jha:
Smart Health Care: An Edge-Side Computing Perspective. IEEE Consumer Electron. Mag. 7(1): 29-37 (2018) - [j201]Ayten Ozge Akmandor, Niraj K. Jha:
Detecting and Alleviating Stress with SoDA. Computer 51(7): 4-5 (2018) - [j200]Hongxu Yin, Ayten Ozge Akmandor, Arsalan Mosenia, Niraj K. Jha:
Smart Healthcare. Found. Trends Electron. Des. Autom. 12(4): 401-466 (2018) - [j199]Ye Yu, Niraj K. Jha:
Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment. ACM J. Emerg. Technol. Comput. Syst. 14(1): 3:1-3:25 (2018) - [j198]Jie Lu, Hongyang Jia, Naveen Verma, Niraj K. Jha:
Genetic Programming for Energy-Efficient and Energy-Scalable Approximate Feature Computation in Embedded Inference Systems. IEEE Trans. Computers 67(2): 222-236 (2018) - [j197]Hongxu Yin, Zeyu Wang, Niraj K. Jha:
A Hierarchical Inference Model for Internet-of-Things. IEEE Trans. Multi Scale Comput. Syst. 4(3): 260-271 (2018) - [j196]Arsalan Mosenia, Niraj K. Jha:
OpSecure: A Secure Unidirectional Optical Channel for Implantable Medical Devices. IEEE Trans. Multi Scale Comput. Syst. 4(3): 410-419 (2018) - [j195]Arsalan Mosenia, Xiaoliang Dai, Prateek Mittal, Niraj K. Jha:
PinMe: Tracking a Smartphone User around the World. IEEE Trans. Multi Scale Comput. Syst. 4(3): 420-435 (2018) - [j194]Ye Yu, Niraj K. Jha:
A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation. IEEE Trans. Multi Scale Comput. Syst. 4(4): 533-547 (2018) - [j193]Ayten Ozge Akmandor, Hongxu Yin, Niraj K. Jha:
Smart, Secure, Yet Energy-Efficient, Internet-of-Things Sensors. IEEE Trans. Multi Scale Comput. Syst. 4(4): 914-930 (2018) - [j192]Abdullah Guler, Niraj K. Jha:
Hybrid Monolithic 3-D IC Floorplanner. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1868-1880 (2018) - [c203]Ayten Ozge Akmandor, Hongxu Yin, Niraj K. Jha:
Simultaneously ensuring smartness, security, and energy efficiency in Internet-of-Things sensors. CICC 2018: 1-8 - [c202]Niraj K. Jha:
Smart healthcare. ICCE 2018: 1 - [c201]Linus Torvalds, Niraj K. Jha, Gary Davis, Nasir D. Memon, Petronel Bigioi, Swarup Bhunia, Koji Nakao:
Keynotes. ICCE 2018: 1-4 - [i4]Arsalan Mosenia, Xiaoliang Dai, Prateek Mittal, Niraj K. Jha:
PinMe: Tracking a Smartphone User around the World. CoRR abs/1802.01468 (2018) - [i3]Xiaoliang Dai, Hongxu Yin, Niraj K. Jha:
Grow and Prune Compact, Fast, and Accurate LSTMs. CoRR abs/1805.11797 (2018) - [i2]Xiaoliang Dai, Peizhao Zhang, Bichen Wu, Hongxu Yin, Fei Sun, Yanghan Wang, Marat Dukhan, Yunqing Hu, Yiming Wu, Yangqing Jia, Peter Vajda, Matt Uyttendaele, Niraj K. Jha:
ChamNet: Towards Efficient Network Design through Platform-Aware Model Adaptation. CoRR abs/1812.08934 (2018) - 2017
- [j191]Mrityunjay Ghosh, Amlan Chakrabarti, Niraj K. Jha:
Automated Quantum Circuit Synthesis and Cost Estimation for the Binary Welded Tree Oracle. ACM J. Emerg. Technol. Comput. Syst. 13(4): 51:1-51:14 (2017) - [j190]Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
CABA: Continuous Authentication Based on BioAura. IEEE Trans. Computers 66(5): 759-772 (2017) - [j189]Arsalan Mosenia, Niraj K. Jha:
A Comprehensive Study of Security of Internet-of-Things. IEEE Trans. Emerg. Top. Comput. 5(4): 586-602 (2017) - [j188]Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
Wearable Medical Sensor-Based System Design: A Survey. IEEE Trans. Multi Scale Comput. Syst. 3(2): 124-138 (2017) - [j187]Hongxu Yin, Niraj K. Jha:
A Health Decision Support System for Disease Diagnosis Based on Wearable Medical Sensors and Machine Learning Ensembles. IEEE Trans. Multi Scale Comput. Syst. 3(4): 228-241 (2017) - [j186]Debajit Bhattacharya, Niraj K. Jha:
Analytical Modeling of the SMART NoC. IEEE Trans. Multi Scale Comput. Syst. 3(4): 242-254 (2017) - [j185]Arsalan Mosenia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
DISASTER: Dedicated Intelligent Security Attacks on Sensor-Triggered Emergency Responses. IEEE Trans. Multi Scale Comput. Syst. 3(4): 255-268 (2017) - [j184]Ayten Ozge Akmandor, Niraj K. Jha:
Keep the Stress Away with SoDA: Stress Detection and Alleviation System. IEEE Trans. Multi Scale Comput. Syst. 3(4): 269-282 (2017) - [j183]Xiaoliang Dai, Niraj K. Jha:
Improving Convergence and Simulation Time of Quantum Hydrodynamic Simulation: Application to Extraction of Best 10-nm FinFET Parameter Values. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 319-329 (2017) - [j182]Xiaoliang Dai, Niraj K. Jha:
Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2616-2624 (2017) - [c200]Niraj K. Jha:
Internet-of-Medical-Things. ACM Great Lakes Symposium on VLSI 2017: 7 - [i1]Xiaoliang Dai, Hongxu Yin, Niraj K. Jha:
NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm. CoRR abs/1711.02017 (2017) - 2016
- [j181]Aoxiang Tang, Xun Gao, Lung-Yen Chen, Niraj K. Jha:
Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes. ACM J. Emerg. Technol. Comput. Syst. 12(4): 42:1-42:21 (2016) - [j180]Sourindra M. Chaudhuri, Niraj K. Jha:
Ultra-Low-Leakage and High-Performance Logic Circuit Design Using Multiparameter Asymmetric FinFETs. ACM J. Emerg. Technol. Comput. Syst. 12(4): 43:1-43:25 (2016) - [j179]Abdullah Guler, Niraj K. Jha:
Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs. ACM J. Emerg. Technol. Comput. Syst. 13(2): 26:1-26:25 (2016) - [j178]Jie Lu, Naveen Verma, Niraj K. Jha:
Compressed Signal Processing on Nyquist-Sampled Signals. IEEE Trans. Computers 65(11): 3293-3303 (2016) - [j177]Debajit Bhattacharya, Niraj K. Jha:
Ultra-High Density Monolithic 3-D FinFET SRAM With Enhanced Read Stability. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1176-1187 (2016) - [j176]Arsalan Mohsen Nia, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
Physiological Information Leakage: A New Frontier in Health Information Security. IEEE Trans. Emerg. Top. Comput. 4(3): 321-334 (2016) - [j175]Debajit Bhattacharya, Niraj K. Jha:
TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 329-333 (2016) - [j174]Aoxiang Tang, Niraj K. Jha:
GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1126-1139 (2016) - [j173]Xianmin Chen, Niraj K. Jha:
A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1649-1662 (2016) - [j172]Xianmin Chen, Niraj K. Jha:
Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3013-3026 (2016) - [c199]Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha:
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism. VLSID 2016: 300-305 - 2015
- [j171]Xianmin Chen, Niraj K. Jha:
gem5-PVT: A Framework for FinFET System Simulation under PVT Variations. ACM J. Emerg. Technol. Comput. Syst. 12(3): 28:1-28:19 (2015) - [j170]Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare. IEEE J. Biomed. Health Informatics 19(6): 1893-1905 (2015) - [j169]Arsalan Mohsen Nia, Mehran Mozaffari Kermani, Susmita Sur-Kolay, Anand Raghunathan, Niraj K. Jha:
Energy-Efficient Long-term Continuous Personal Health Monitoring. IEEE Trans. Multi Scale Comput. Syst. 1(2): 85-98 (2015) - [j168]Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
Signal Processing With Direct Computations on Compressively Sensed Data. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 30-43 (2015) - [j167]Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha:
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 963-967 (2015) - [j166]Chia-Chun Lin, Susmita Sur-Kolay, Niraj K. Jha:
PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1221-1234 (2015) - [j165]Aoxiang Tang, Yang Yang, Chun-Yi Lee, Niraj K. Jha:
McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations. IEEE Trans. Very Large Scale Integr. Syst. 23(9): 1616-1627 (2015) - [j164]Ting-Jung Lin, Wei Zhang, Niraj K. Jha:
FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 1987-2000 (2015) - [c198]Younghyun Kim, Woo Suk Lee, Vijay Raghunathan, Niraj K. Jha, Anand Raghunathan:
Vibration-based secure side channel for medical devices. DAC 2015: 32:1-32:6 - [c197]Philipp Niemann, Saikat Basu, Amlan Chakrabarti, Niraj K. Jha, Robert Wille:
Synthesis of Quantum Circuits for Dedicated Physical Machine Descriptions. RC 2015: 248-264 - 2014
- [j163]Meng Zhang, Anand Raghunathan, Niraj K. Jha:
A defense framework against malware and vulnerability exploits. Int. J. Inf. Sec. 13(5): 439-452 (2014) - [j162]Chia-Chun Lin, Niraj K. Jha:
RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits. ACM J. Emerg. Technol. Comput. Syst. 10(2): 14:1-14:25 (2014) - [j161]Sourindra Chaudhuri, Niraj K. Jha:
3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations. ACM J. Emerg. Technol. Comput. Syst. 10(3): 26:1-26:19 (2014) - [j160]Xianmin Chen, Niraj K. Jha:
Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles. ACM J. Emerg. Technol. Comput. Syst. 11(1): 3:1-3:16 (2014) - [j159]Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha:
QLib: Quantum module library. ACM J. Emerg. Technol. Comput. Syst. 11(1): 7:1-7:20 (2014) - [j158]Sourindra M. Chaudhuri, Prateek Mishra, Niraj K. Jha:
Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology. ACM J. Emerg. Technol. Comput. Syst. 11(2): 19:1-19:20 (2014) - [j157]Meng Zhang, Anand Raghunathan, Niraj K. Jha:
Trustworthiness of Medical Devices and Body Area Networks. Proc. IEEE 102(8): 1174-1188 (2014) - [j156]Mohammed Shoaib, Kyong-Ho Lee, Niraj K. Jha, Naveen Verma:
A 0.6-107 µW Energy-Scalable Processor for Directly Analyzing Compressively-Sensed EEG. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1105-1118 (2014) - [j155]Ajay N. Bhoj, Niraj K. Jha:
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22(3): 548-561 (2014) - [j154]Chun-Yi Lee, Niraj K. Jha:
FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1150-1163 (2014) - [j153]Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha:
FTQLS: Fault-Tolerant Quantum Logic Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1350-1363 (2014) - [j152]Yang Yang, Niraj K. Jha:
FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2462-2475 (2014) - [j151]Ting-Jung Lin, Wei Zhang, Niraj K. Jha:
A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps. IEEE Trans. Very Large Scale Integr. Syst. 22(12): 2607-2620 (2014) - [c196]Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha:
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. CICC 2014: 1-4 - [c195]Sourindra Chaudhuri, Niraj K. Jha:
FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply Voltage. VLSID 2014: 476-482 - 2013
- [j150]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
Improving the Trustworthiness of Medical Device Software with Formal Verification Methods. IEEE Embed. Syst. Lett. 5(3): 50-53 (2013) - [j149]Aoxiang Tang, Niraj K. Jha:
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits. ACM J. Emerg. Technol. Comput. Syst. 9(1): 6:1-6:16 (2013) - [j148]Aoxiang Tang, Niraj K. Jha:
Design space exploration of FinFET cache. ACM J. Emerg. Technol. Comput. Syst. 9(3): 20:1-20:16 (2013) - [j147]Meng Zhang, Anand Raghunathan, Niraj K. Jha:
MedMon: Securing Medical Devices Through Wireless Monitoring and Anomaly Detection. IEEE Trans. Biomed. Circuits Syst. 7(6): 871-881 (2013) - [j146]Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha:
Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(1): 47-58 (2013) - [j145]Chun-Yi Lee, Niraj K. Jha:
Variable-Pipeline-Stage Router. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1669-1682 (2013) - [j144]Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors. IEEE Trans. Very Large Scale Integr. Syst. 21(10): 1849-1862 (2013) - [j143]Ajay N. Bhoj, Niraj K. Jha:
Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 1975-1988 (2013) - [j142]Chia-Chun Lin, Amlan Chakrabarti, Niraj K. Jha:
Optimized Quantum Gate Library for Various Physical Machine Descriptions. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2055-2068 (2013) - [j141]Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha:
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. IEEE Trans. Very Large Scale Integr. Syst. 21(11): 2094-2105 (2013) - [c194]Meng Zhang, Anand Raghunathan, Niraj K. Jha:
Towards trustworthy medical devices and body area networks. DAC 2013: 14:1-14:6 - [c193]Jun Wei Chuah, Chunxiao Li, Niraj K. Jha, Anand Raghunathan:
Localized Heating for Building Energy Efficiency. VLSI Design 2013: 13-18 - [c192]Meng Zhang, Mehran Mozaffari Kermani, Anand Raghunathan, Niraj K. Jha:
Energy-efficient and Secure Sensor Data Transmission Using Encompression. VLSI Design 2013: 31-36 - [c191]Neeraj Mishra, Niraj K. Jha, Santanu Kapat, Amit Patra:
Embedded Reconfigurable Augmented DC-DC Boost Converter for Fast Transient Recovery. VLSI Design 2013: 147-152 - [c190]Mehran Mozaffari Kermani, Meng Zhang, Anand Raghunathan, Niraj K. Jha:
Emerging Frontiers in Embedded Security. VLSI Design 2013: 203-208 - [c189]Yang Yang, Niraj K. Jha:
Fin Prin: Analysis and Optimization of FinFET Logic Circuits under PVT Variations. VLSI Design 2013: 350-355 - 2012
- [j140]Chunxiao Li, Niraj K. Jha, Anand Raghunathan:
Secure reconfiguration of software-defined radio. ACM Trans. Embed. Comput. Syst. 11(1): 10:1-10:22 (2012) - [j139]Divya Arora, Najwa Aaraj, Anand Raghunathan, Niraj K. Jha:
INVISIOS: A Lightweight, Minimally Intrusive Secure Execution Environment. ACM Trans. Embed. Comput. Syst. 11(3): 60:1-60:20 (2012) - [j138]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
A Trusted Virtual Machine in an Untrusted Management Environment. IEEE Trans. Serv. Comput. 5(4): 472-483 (2012) - [j137]Ting-Jung Lin, Wei Zhang, Niraj K. Jha:
SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2151-2156 (2012) - [c188]Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
A compressed-domain processor for seizure detection to simultaneously reduce computation and communication energy. CICC 2012: 1-4 - [c187]Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals. DATE 2012: 437-442 - [c186]Amlan Chakrabarti, Chia-Chun Lin, Niraj K. Jha:
Design of Quantum Circuits for Random Walk Algorithms. ISVLSI 2012: 135-140 - [c185]Sourindra Chaudhuri, Prateek Mishra, Niraj K. Jha:
Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology. VLSI Design 2012: 238-244 - 2011
- [j136]Meng Zhang, Niraj K. Jha:
FinFET-Based Power Management for Improved DPA Resistance with Low Overhead. ACM J. Emerg. Technol. Comput. Syst. 7(3): 10:1-10:16 (2011) - [j135]Najwa Aaraj, Anand Raghunathan, Niraj K. Jha:
A framework for defending embedded systems against software attacks. ACM Trans. Embed. Comput. Syst. 10(3): 33:1-33:23 (2011) - [j134]Niraj K. Jha:
Editorial Announcing a New Editor-in-Chief. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 173-174 (2011) - [c184]Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
A low-energy computation platform for data-driven biomedical monitoring algorithms. DAC 2011: 591-596 - [c183]Chun-Yi Lee, Niraj K. Jha:
CACTI-FinFET: an integrated delay and power modeling framework for FinFET-based caches under process variations. DAC 2011: 866-871 - [c182]Sourindra Chaudhuri, Niraj K. Jha:
3D vs. 2D analysis of FinFET logic gates under process variations. ICCD 2011: 435-436 - [c181]Ajay N. Bhoj, Niraj K. Jha:
Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology. ISQED 2011: 695-702 - 2010
- [j133]Chun-Yi Lee, Niraj K. Jha:
FinFET-based power simulator for interconnection networks. ACM J. Emerg. Technol. Comput. Syst. 6(1): 2:1-2:18 (2010) - [j132]Wei Zhang, Niraj K. Jha, Li Shang:
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture. ACM J. Emerg. Technol. Comput. Syst. 6(3): 10:1-10:32 (2010) - [j131]Ajay N. Bhoj, Niraj K. Jha:
Gated-diode FinFET DRAMs: Device and circuit design-considerations. ACM J. Emerg. Technol. Comput. Syst. 6(4): 12:1-12:32 (2010) - [j130]Niraj K. Jha:
Editorial: New Associate Editor Appointments. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 345-346 (2010) - [c180]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
A Secure User Interface for Web Applications Running Under an Untrusted Operating System. CIT 2010: 865-870 - [c179]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
Secure Virtual Machine Execution under an Untrusted Management OS. IEEE CLOUD 2010: 172-179 - [c178]Prateek Mishra, Niraj K. Jha:
Low-power FinFET circuit synthesis using surface orientation optimization. DATE 2010: 311-314 - [c177]Prateek Mishra, Ajay N. Bhoj, Niraj K. Jha:
Die-level leakage power analysis of FinFET circuits considering process variations. ISQED 2010: 347-355 - [c176]Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha:
Fault modeling for FinFET circuits. NANOARCH 2010: 41-46 - [c175]Muzaffer O. Simsir, Niraj K. Jha:
NanoV: Nanowire-based VLSI design. NANOARCH 2010: 53-58
2000 – 2009
- 2009
- [j129]Prateek Mishra, Anish Muttreja, Niraj K. Jha:
Low-power FinFET circuit synthesis using multiple supply and threshold voltages. ACM J. Emerg. Technol. Comput. Syst. 5(2): 7:1-7:23 (2009) - [j128]Wei Zhang, Niraj K. Jha, Li Shang:
A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow. ACM J. Emerg. Technol. Comput. Syst. 5(3): 13:1-13:31 (2009) - [j127]Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha:
A hybrid nano-CMOS architecture for defect and fault tolerance. ACM J. Emerg. Technol. Comput. Syst. 5(3): 14:1-14:26 (2009) - [j126]Wei Zhang, Niraj K. Jha, Li Shang:
A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture. ACM J. Emerg. Technol. Comput. Syst. 5(4): 16:1-16:30 (2009) - [j125]Wei Zhang, Niraj K. Jha, Li Shang:
Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture. ACM J. Emerg. Technol. Comput. Syst. 5(4): 17:1-17:27 (2009) - [j124]Niraj K. Jha:
Editorial Appointments for the 2009-2010 Term. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 453-469 (2009) - [j123]Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty:
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 697-708 (2009) - [c174]Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
An architecture for secure software defined radio. DATE 2009: 448-453 - [c173]Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha:
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects. HPCA 2009: 67-78 - [c172]Chun-Yi Lee, Niraj K. Jha:
FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing. ICCD 2009: 350-357 - [c171]Ajay N. Bhoj, Niraj K. Jha:
Pragmatic design of gated-diode FinFET DRAMs. ICCD 2009: 390-397 - [c170]Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha:
GARNET: A detailed on-chip network model inside a full-system simulator. ISPASS 2009: 33-42 - [c169]Muzaffer O. Simsir, Niraj K. Jha:
Thermal characterization of BIST, scan design and sequential test methodologies. ITC 2009: 1-9 - [c168]Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha:
In-network coherence filtering: snoopy coherence without broadcasts. MICRO 2009: 232-243 - 2008
- [j122]James Donald, Niraj K. Jha:
Reversible logic synthesis with Fredkin and Peres gates. ACM J. Emerg. Technol. Comput. Syst. 4(1): 2:1-2:19 (2008) - [j121]Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha:
Toward Ideal On-Chip Communication Using Express Virtual Channels. IEEE Micro 28(1): 80-90 (2008) - [j120]Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha:
System-Level Dynamic Thermal Management for High-Performance Microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 96-108 (2008) - [j119]Yunsi Fei, Lin Zhong, Niraj K. Jha:
An energy-aware framework for dynamic software management in mobile computing systems. ACM Trans. Embed. Comput. Syst. 7(3): 27:1-27:31 (2008) - [j118]Najwa Aaraj, Anand Raghunathan, Niraj K. Jha:
Analysis and design of a hardware/software trusted platform module for embedded systems. ACM Trans. Embed. Comput. Syst. 8(1): 8:1-8:31 (2008) - [j117]Pallav Gupta, Rui Zhang, Niraj K. Jha:
Automatic Test Generation for Combinational Threshold Logic Networks. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 1035-1045 (2008) - [c167]Najwa Aaraj, Anand Raghunathan, Niraj K. Jha:
Dynamic Binary Instrumentation-Based Framework for Malware Defense. DIMVA 2008: 64-87 - [c166]Amit Kumar, Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha:
A system-level perspective for efficient NoC design. IPDPS 2008: 1-5 - [c165]Amit Kumar, Li-Shiuan Peh, Niraj K. Jha:
Token flow control. MICRO 2008: 342-353 - [c164]Prateek Mishra, Anish Muttreja, Niraj K. Jha:
Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis. NANOARCH 2008: 77-84 - [c163]Anish Muttreja, Prateek Mishra, Niraj K. Jha:
Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. VLSI Design 2008: 220-227 - [c162]Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha:
Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture. VLSI Design 2008: 435-440 - [c161]Anish Muttreja, Srivaths Ravi, Niraj K. Jha:
Variability-Tolerant Register-Transfer Level Synthesis. VLSI Design 2008: 621-628 - 2007
- [j116]Li Shang, Robert P. Dick, Niraj K. Jha:
SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 508-526 (2007) - [j115]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Automated Energy/Performance Macromodeling of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 542-552 (2007) - [j114]Jiong Luo, Niraj K. Jha:
Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6): 1161-1170 (2007) - [j113]Rui Zhang, Pallav Gupta, Niraj K. Jha:
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1233-1245 (2007) - [j112]Loganathan Lingappan, Niraj K. Jha:
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1339-1345 (2007) - [j111]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Hybrid Simulation for Energy Estimation of Embedded Software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10): 1843-1854 (2007) - [j110]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 2035-2045 (2007) - [j109]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy-optimizing source code transformations for operating system-driven embedded software. ACM Trans. Embed. Comput. Syst. 7(1): 2:1-2:26 (2007) - [j108]Pallav Gupta, Niraj K. Jha, Loganathan Lingappan:
A Test Generation Framework for Quantum Cellular Automata Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(1): 24-36 (2007) - [j107]Niraj K. Jha:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 15(3): 249-261 (2007) - [j106]Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 15(3): 296-308 (2007) - [j105]Jiong Luo, Niraj K. Jha, Li-Shiuan Peh:
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 427-437 (2007) - [j104]Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee:
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 465-470 (2007) - [j103]Loganathan Lingappan, Niraj K. Jha:
Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 518-530 (2007) - [j102]Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Architectural Support for Run-Time Validation of Program Data Properties. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 546-559 (2007) - [j101]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha:
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 605-609 (2007) - [j100]Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC. IEEE Trans. Very Large Scale Integr. Syst. 15(6): 699-710 (2007) - [j99]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1191-1204 (2007) - [c160]Le Yan, Lin Zhong, Niraj K. Jha:
Energy comparison and optimization of wireless body-area network technologies. BODYNETS 2007: 8 - [c159]Wei Zhang, Li Shang, Niraj K. Jha:
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. DAC 2007: 300-305 - [c158]Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Energy and execution time analysis of a software-based trusted platform module. DATE 2007: 1128-1133 - [c157]Amit Kumar, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha:
A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. ICCD 2007: 63-70 - [c156]Anish Muttreja, Niket Agarwal, Niraj K. Jha:
CMOS logic design with independent-gate FinFETs. ICCD 2007: 560-567 - [c155]Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha:
Express virtual channels: towards the ideal interconnection fabric. ISCA 2007: 150-161 - [c154]Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha:
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. VLSI Design 2007: 504-512 - 2006
- [j98]Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha:
Temperature-Aware On-Chip Networks. IEEE Micro 26(1): 130-139 (2006) - [j97]Li Shang, Li-Shiuan Peh, Niraj K. Jha:
PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 92-110 (2006) - [j96]Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 544-557 (2006) - [j95]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Application-specific heterogeneous multiprocessor synthesis using extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1589-1602 (2006) - [j94]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Use of Computation-Unit Integrated Memories in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 1969-1989 (2006) - [j93]Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
RTL-Aware Cycle-Accurate Functional Power Estimation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2103-2117 (2006) - [j92]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2193-2206 (2006) - [j91]Pallav Gupta, Abhinav Agrawal, Niraj K. Jha:
An Algorithm for Synthesis of Reversible Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2317-2330 (2006) - [j90]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols. IEEE Trans. Mob. Comput. 5(2): 128-143 (2006) - [j89]Keith S. Vallerio, Lin Zhong, Niraj K. Jha:
Energy-Efficient Graphical User Interface Design. IEEE Trans. Mob. Comput. 5(7): 846-859 (2006) - [j88]Lin Zhong, Niraj K. Jha:
Dynamic Power Optimization Targeting User Delays in Interactive Systems. IEEE Trans. Mob. Comput. 5(11): 1473-1488 (2006) - [j87]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Scalable Synthesis Methodology for Application-Specific Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1175-1188 (2006) - [j86]Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(12): 1295-1308 (2006) - [c153]Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Architectural support for safe software execution on embedded processors. CODES+ISSS 2006: 106-111 - [c152]Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar:
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC. DAC 2006: 496-501 - [c151]Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha:
HybDTM: a coordinated hardware-software approach for dynamic thermal management. DAC 2006: 548-553 - [c150]Wei Zhang, Niraj K. Jha, Li Shang:
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. DAC 2006: 711-716 - [c149]Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Architectures for efficient face authentication in embedded systems. DATE Designers' Forum 2006: 1-6 - [c148]Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee:
Satisfiability-based framework for enabling side-channel attacks on cryptographic software. DATE Designers' Forum 2006: 18-23 - [c147]Pallav Gupta, Niraj K. Jha, Loganathan Lingappan:
Test generation for combinational quantum cellular automata (QCA) circuits. DATE 2006: 311-316 - [c146]Rui Zhang, Niraj K. Jha:
Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. ACM Great Lakes Symposium on VLSI 2006: 8-13 - [c145]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Active Learning Driven Data Acquisition for Sensor Networks. ISCC 2006: 929-934 - [c144]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha:
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors. VLSI Design 2006: 299-304 - [c143]Rui Zhang, Niraj K. Jha:
State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. VLSI Design 2006: 317-322 - [c142]Loganathan Lingappan, Niraj K. Jha:
Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults. VLSI Design 2006: 431-436 - [c141]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors. VLSI Design 2006: 473-476 - 2005
- [j85]Yunsi Fei, Niraj K. Jha:
Integrated functional partitioning and synthesis for low power distributed systems of systems-on-a-chip. Int. J. Embed. Syst. 1(1/2): 2-13 (2005) - [j84]Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha:
Threshold network synthesis and optimization and its application to nanotechnologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1): 107-118 (2005) - [j83]Lin Zhong, Niraj K. Jha:
Interconnect-aware low-power high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 336-351 (2005) - [j82]Le Yan, Jiong Luo, Niraj K. Jha:
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1030-1041 (2005) - [j81]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input space-adaptive optimization for embedded-software synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1677-1693 (2005) - [j80]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Generation of distributed logic-memory architectures through high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1694-1711 (2005) - [j79]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
Energy macromodeling of embedded operating systems. ACM Trans. Embed. Comput. Syst. 4(1): 231-254 (2005) - [j78]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
Memory binding for performance optimization of control-flow intensive behavioral descriptions. IEEE Trans. Very Large Scale Integr. Syst. 13(5): 513-524 (2005) - [c140]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory. CICC 2005: 239-242 - [c139]Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Enhancing security through hardware-assisted run-time validation of program data properties. CODES+ISSS 2005: 190-195 - [c138]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Hybrid simulation for embedded software energy estimation. DAC 2005: 23-26 - [c137]Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Efficient fingerprint-based user authentication for embedded systems. DAC 2005: 244-247 - [c136]Le Yan, Lin Zhong, Niraj K. Jha:
User-perceived latency driven voltage scaling for interactive applications. DAC 2005: 624-627 - [c135]Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. DATE 2005: 178-183 - [c134]Niraj K. Jha:
Nanotechnology in the Service of Embedded and Ubiquitous Computing. EUC 2005: 1 - [c133]Wei Zhang, Niraj K. Jha:
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. ICCD 2005: 281-288 - [c132]Le Yan, Lin Zhong, Niraj K. Jha:
Towards a Responsive, Yet Power-ef.cient, Operating System: A Holistic Approach. MASCOTS 2005: 249-257 - [c131]Lin Zhong, Mike Sinclair, Niraj K. Jha:
A personal-area network of low-power wireless interfacing devices for handhelds: system and hardware design. Mobile HCI 2005: 251-254 - [c130]Lin Zhong, Niraj K. Jha:
Energy efficiency of handheld computer interfaces: limits, characterization and practice. MobiSys 2005: 247-260 - [c129]Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar:
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip. VLSI Design 2005: 65-70 - [c128]Rui Zhang, Pallav Gupta, Niraj K. Jha:
Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. VLSI Design 2005: 229-234 - [c127]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors. VLSI Design 2005: 551-556 - [c126]Loganathan Lingappan, Niraj K. Jha:
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. VTS 2005: 418-423 - 2004
- [j77]Robert P. Dick, Niraj K. Jha:
COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 2-16 (2004) - [j76]Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey:
Common-case computation: a high-level energy and performance optimization technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1): 33-49 (2004) - [j75]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Custom-instruction synthesis for extensible-processor platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 216-228 (2004) - [j74]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A hybrid energy-estimation technique for extensible processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 652-664 (2004) - [j73]Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Resource budgeting for Multiprocess High-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1010-1019 (2004) - [j72]Jiong Luo, Lin Zhong, Yunsi Fei, Niraj K. Jha:
Register binding-based RTL power management for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1175-1183 (2004) - [j71]Li Shang, Robert P. Dick, Niraj K. Jha:
DESP: A Distributed Economics-Based Subcontracting Protocol for Computation Distribution in Power-Aware Mobile Ad Hoc Networks. IEEE Trans. Mob. Comput. 3(1): 33-45 (2004) - [j70]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input space adaptive design: a high-level methodology for optimizing energy and performance. IEEE Trans. Very Large Scale Integr. Syst. 12(6): 590-602 (2004) - [c125]Keith S. Vallerio, Niraj K. Jha:
Evaluating Conditional Statements in Embedded System Software: Systematic Methodologies for Reducing Energy Consumption. ESA/VLSI 2004: 63-69 - [c124]Keith S. Vallerio, Niraj K. Jha:
Language Selection for Mobile Systems: Java, C, or Both? ESA/VLSI 2004: 185-191 - [c123]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software. ESA/VLSI 2004: 601-605 - [c122]Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Automated energy/performance macromodeling of embedded software. DAC 2004: 99-102 - [c121]Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha:
Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. DATE 2004: 904-909 - [c120]Pallav Gupta, Niraj K. Jha:
An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. DATE 2004: 974-979 - [c119]Abhinav Agrawal, Niraj K. Jha:
Synthesis of Reversible Logic. DATE 2004: 1384-1385 - [c118]Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Power estimation for cycle-accurate functional descriptions of hardware. ICCAD 2004: 668-675 - [c117]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
High-level synthesis using computation-unit integrated memories. ICCAD 2004: 783-790 - [c116]Pallav Gupta, Rui Zhang, Niraj K. Jha:
An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. ICCD 2004: 540-543 - [c115]Keith S. Vallerio, Lin Zhong, Niraj K. Jha:
Energy-Efficient Graphical User Interface Design. International Conference on Wireless Networks 2004: 959-962 - [c114]Yunsi Fei, Lin Zhong, Niraj K. Jha:
An Energy-Aware Framework for Coordinated Dynamic Software Management in Mobile Computers. MASCOTS 2004: 306-317 - [c113]Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha:
Thermal Modeling, Characterization and Management of On-Chip Networks. MICRO 2004: 67-78 - [c112]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. VLSI Design 2004: 261-266 - [c111]Weidong Wang, Anand Raghunathan, Niraj K. Jha:
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. VLSI Design 2004: 267- - [c110]Lin Zhong, Niraj K. Jha:
Dynamic Power Optimization of Interactive Systems. VLSI Design 2004: 1041-1047 - [e1]Laurence Tianruo Yang, Minyi Guo, Guang R. Gao, Niraj K. Jha:
Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings. Lecture Notes in Computer Science 3207, Springer 2004, ISBN 3-540-22906-X [contents] - 2003
- [j69]Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Analysis of power dissipation in embedded systems using real-time operating systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 615-627 (2003) - [j68]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
A simulation framework for energy-consumption analysis of OS-driven embedded applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(9): 1284-1294 (2003) - [j67]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
High-level macro-modeling and estimation techniques for switching activity and power consumption. IEEE Trans. Very Large Scale Integr. Syst. 11(4): 538-557 (2003) - [c109]Lin Zhong, Niraj K. Jha:
Graphical user interface energy characterization for handheld computers. CASES 2003: 232-242 - [c108]Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy Estimation for Extensible Processors. DATE 2003: 10682-10687 - [c107]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
Software Architectural Transformations: A New Approach to Low Energy Embedded Software. DATE 2003: 11046-11051 - [c106]Jiong Luo, Li-Shiuan Peh, Niraj K. Jha:
Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems. DATE 2003: 11150-11151 - [c105]Weidong Wang, Tat Kee Tan, Jiong Luo, Yunsi Fei, Li Shang, Keith S. Vallerio, Lin Zhong, Anand Raghunathan, Niraj K. Jha:
A comprehensive high-level synthesis system for control-flow intensive behaviors. ACM Great Lakes Symposium on VLSI 2003: 11-14 - [c104]Li Shang, Li-Shiuan Peh, Niraj K. Jha:
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. HPCA 2003: 91-102 - [c103]Le Yan, Jiong Luo, Niraj K. Jha:
Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Heterogeneous Distributed Real-time Embedded Systems. ICCAD 2003: 30-38 - [c102]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications. ICCAD 2003: 46-53 - [c101]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
A Scalable Application-Specific Processor Synthesis Methodology. ICCAD 2003: 283-290 - [c100]Pallav Gupta, Lin Zhong, Niraj K. Jha:
A High-level Interconnect Power Model for Design Space Exploration. ICCAD 2003: 551-559 - [c99]Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha:
Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. ICCD 2003: 187-193 - [c98]Li Shang, Li-Shiuan Peh, Niraj K. Jha:
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks. ICS 2003: 98-108 - [c97]Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Analyzing the energy consumption of security protocols. ISLPED 2003: 30-35 - [c96]Jiong Luo, Niraj K. Jha:
Power-profile Driven Variable Voltage Sealing for Heterogeneous Distributed Real-time Embedded Systems. VLSI Design 2003: 369-375 - [c95]Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey:
High-level Synthesis of Multi-process Behavioral Descriptions. VLSI Design 2003: 467-473 - [c94]Keith S. Vallerio, Niraj K. Jha:
Task Graph Extraction for Embedded System Synthesis. VLSI Design 2003: 480- - [p1]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
Software Architectural Transformations. Embedded Software for SoC 2003: 467-484 - 2002
- [j66]Li Shang, Li-Shiuan Peh, Niraj K. Jha:
Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links. IEEE Comput. Archit. Lett. 1 (2002) - [j65]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
High-level test compaction techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 827-841 (2002) - [j64]Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
High-level energy macromodeling of embedded software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1037-1050 (2002) - [j63]Srivaths Ravi, Niraj K. Jha:
Test synthesis of systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1211-1217 (2002) - [j62]Kamal S. Khouri, Niraj K. Jha:
Leakage power analysis and reduction during behavioral synthesis. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 876-885 (2002) - [c93]Jiong Luo, Niraj K. Jha:
Low Power Distributed Embedded Systems: Dynamic Voltage Scaling and Synthesis. HiPC 2002: 679-692 - [c92]Lin Zhong, Niraj K. Jha:
Interconnect-aware high-level synthesis for low power. ICCAD 2002: 110-117 - [c91]Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
High-level synthesis of distributed logic-memory architectures. ICCAD 2002: 564-571 - [c90]Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Synthesis of custom processors based on extensible platforms. ICCAD 2002: 641-648 - [c89]Lin Zhong, Jiong Luo, Yunsi Fei, Niraj K. Jha:
Register Binding Based Power Management for High-level Synthesis of Control-Flow Intensive Behaviors. ICCD 2002: 391-394 - [c88]Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
Embedded Operating System Energy Analysis and Macro-Modeling. ICCD 2002: 515-520 - [c87]Keith S. Vallerio, Niraj K. Jha:
Task graph transformation to aid system synthesis. ISCAS (4) 2002: 695-698 - [c86]Li Shang, Robert P. Dick, Niraj K. Jha:
An Economics-based Power-aware Protocol for Computation Distribution in Mobile Ad-Hoc Networks. IASTED PDCS 2002: 339-344 - [c85]Yunsi Fei, Niraj K. Jha:
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip. ASP-DAC/VLSI Design 2002: 274-281 - [c84]Li Shang, Niraj K. Jha:
Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. ASP-DAC/VLSI Design 2002: 345- - [c83]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input Space Adaptive Embedded Software Synthesis. ASP-DAC/VLSI Design 2002: 711-718 - [c82]Jiong Luo, Niraj K. Jha:
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. ASP-DAC/VLSI Design 2002: 719- - 2001
- [j61]Kamal S. Khouri, Niraj K. Jha:
Clock selection for performance optimization of control-flowintensive behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 158-165 (2001) - [j60]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
Testing of core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 426-439 (2001) - [j59]Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha:
Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1414-1425 (2001) - [j58]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO: regular expression-based register-transfer level testability analysis and optimization. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 824-832 (2001) - [c81]Jiong Luo, Niraj K. Jha:
Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems. DAC 2001: 444-449 - [c80]Tat Kee Tan, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
High-level Software Energy Macro-modeling. DAC 2001: 605-610 - [c79]Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization. DAC 2001: 738-743 - [c78]Niraj K. Jha:
Low Power System Scheduling and Synthesis. ICCAD 2001: 259-263 - [c77]Li Shang, Niraj K. Jha:
High-Level Power Modeling of CPLDs and FPGAs. ICCD 2001: 46-53 - [c76]Srivaths Ravi, Niraj K. Jha:
Fast test generation for circuits with RTL and gate-level views. ITC 2001: 1068-1077 - [c75]Srivaths Ravi, Niraj K. Jha:
Synthesis of System-on-a-chip for Testability. VLSI Design 2001: 149-156 - 2000
- [j57]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis. IEEE Trans. Computers 49(9): 865-885 (2000) - [j56]Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik:
A BIST scheme for RTL circuits based on symbolic testabilityanalysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 111-128 (2000) - [j55]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 308-324 (2000) - [j54]Indradeep Ghosh, Sujit Dey, Niraj K. Jha:
A fast and low-cost testing technique for core-based system-chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 863-877 (2000) - [j53]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 894-906 (2000) - [c74]Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Power analysis of embedded operating systems. DAC 2000: 312-315 - [c73]Jiong Luo, Niraj K. Jha:
Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. ICCAD 2000: 357-364 - [c72]Kamal S. Khouri, Niraj K. Jha:
Leakage Power Analysis and Reduction during Behavioral Synthesis. ICCD 2000: 561-564 - [c71]Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana:
A Technique for Identifying RTL and Gate-Level Correspondences. ICCD 2000: 591-594 - [c70]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
: Reducing test application time in high-level test generation. ITC 2000: 829-838 - [c69]Robert P. Dick, Niraj K. Jha:
COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems. VLSI Design 2000: 114- - [c68]Kamal S. Khouri, Niraj K. Jha:
Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. VLSI Design 2000: 523-529
1990 – 1999
- 1999
- [j52]Bharat P. Dave, Niraj K. Jha:
COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems. IEEE Trans. Computers 48(4): 417-441 (1999) - [j51]Ganesh Lakshminarayana, Niraj K. Jha:
High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 265-281 (1999) - [j50]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Hierarchical test generation and design for testability methods for ASPPs and ASIPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 357-370 (1999) - [j49]Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha:
Wavesched: a novel scheduling technique for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5): 505-523 (1999) - [j48]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Register transfer level power optimization with emphasis on glitch analysis and reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8): 1114-1131 (1999) - [j47]Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi:
Controller-based power management for control-flow intensive designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1496-1508 (1999) - [j46]Robert P. Dick, Niraj K. Jha:
Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(10): 1527-1527 (1999) - [j45]Ganesh Lakshminarayana, Niraj K. Jha:
FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1577-1594 (1999) - [j44]Indradeep Ghosh, Niraj K. Jha, Sujit Dey:
A low overhead design for testability and test generation technique for core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1661-1676 (1999) - [j43]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
High-level synthesis of low-power control-flow intensive circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(12): 1715-1729 (1999) - [j42]Santhanam Srinivasan, Niraj K. Jha:
Safety and Reliability Driven Task Allocation in Distributed Systems. IEEE Trans. Parallel Distributed Syst. 10(3): 238-251 (1999) - [j41]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Power management in high-level synthesis. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 7-15 (1999) - [j40]Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha:
COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 92-104 (1999) - [c67]Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey:
Common-Case Computation: A High-Level Technique for Power and Performance Optimization. DAC 1999: 56-61 - [c66]Robert P. Dick, Niraj K. Jha:
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis. DATE 1999: 263-270 - [c65]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
A framework for testing core-based systems-on-a-chip. ICCAD 1999: 385-390 - [c64]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
Memory binding for performance optimization of control-flow intensive behaviors. ICCAD 1999: 482-488 - [c63]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST. VTS 1999: 398-406 - 1998
- [b1]Anand Raghunathan, Niraj K. Jha, Sujit Dey:
High-Level Power Analysis and Optimization. Kluwer 1998, ISBN 978-0-7923-8073-3, pp. I-XVI, 1-157 - [j39]Niraj K. Jha:
Guest Editorial. J. Electron. Test. 13(2): 77 (1998) - [j38]Indradeep Ghosh, Niraj K. Jha:
High-level test synthesis: a survey. Integr. 26(1-2): 79-99 (1998) - [j37]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
A design-for-testability technique for register-transfer level circuits using control/data flow extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 706-723 (1998) - [j36]Bharat P. Dave, Niraj K. Jha:
COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 900-919 (1998) - [j35]Robert P. Dick, Niraj K. Jha:
MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 920-935 (1998) - [j34]Sandeep Bhatia, Niraj K. Jha:
Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 608-619 (1998) - [c62]Ganesh Lakshminarayana, Niraj K. Jha:
FACT: A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions. DAC 1998: 102-107 - [c61]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. DAC 1998: 108-113 - [c60]Ganesh Lakshminarayana, Niraj K. Jha:
Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. DAC 1998: 439-444 - [c59]Indradeep Ghosh, Sujit Dey, Niraj K. Jha:
A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. DAC 1998: 542-547 - [c58]Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik:
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. DAC 1998: 554-559 - [c57]Bharat P. Dave, Niraj K. Jha:
CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. DATE 1998: 118-124 - [c56]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. DATE 1998: 848-854 - [c55]Robert P. Dick, Niraj K. Jha:
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems. ICCAD 1998: 62-67 - [c54]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions. ICCAD 1998: 577-584 - [c53]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
Transforming control-flow intensive designs to facilitate power management. ICCAD 1998: 657-664 - [c52]Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
Fast high-level power estimation for control-flow intensive design. ISLPED 1998: 299-304 - [c51]Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha:
TAO: regular expression based high-level testability analysis and optimization. ITC 1998: 331-340 - [c50]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
A Power Management Methodology for High-Level Synthesis. VLSI Design 1998: 24-19 - [c49]Bharat P. Dave, Niraj K. Jha:
COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. VLSI Design 1998: 347-354 - 1997
- [j33]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 1001-1014 (1997) - [j32]Anand Raghunathan, Niraj K. Jha:
SCALP: an iterative-improvement-based low-power data path synthesis system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1260-1277 (1997) - [j31]Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng:
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(12): 1514-1521 (1997) - [j30]Shalini Yajnik, Niraj K. Jha:
Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. IEEE Trans. Parallel Distributed Syst. 8(2): 137-153 (1997) - [j29]Shalini Yajnik, Niraj K. Jha:
Analysis and Randomized Design of Algorithm-Based Fault Tolerant Multiprocessor Systems Under an Extended Model. IEEE Trans. Parallel Distributed Syst. 8(7): 757-768 (1997) - [c48]Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Power Management Techniques for Control-Flow Intensive Designs. DAC 1997: 429-434 - [c47]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. DAC 1997: 534-539 - [c46]Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha:
COSYN: Hardware-Software Co-Synthesis of Embedded Systems. DAC 1997: 703-708 - [c45]Bharat P. Dave, Niraj K. Jha:
COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded System Architectures for Low Overhead Fault Tolerance. FTCS 1997: 339-348 - [c44]Ganesh Lakshminarayana, Kamal S. Khouri, Niraj K. Jha:
Wavesched: a novel scheduling technique for control-flow intensive behavioral descriptions. ICCAD 1997: 244-250 - [c43]Robert P. Dick, Niraj K. Jha:
MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems. ICCAD 1997: 522-529 - [c42]Indradeep Ghosh, Niraj K. Jha, Sujit Dey:
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. ITC 1997: 50-59 - 1996
- [j28]Sandeep Bhatia, Niraj K. Jha:
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 228-243 (1996) - [c41]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Glitch Analysis and Reduction in Register Transfer Level. DAC 1996: 331-336 - [c40]Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis. FTCS 1996: 336-345 - [c39]Anand Raghunathan, Sujit Dey, Niraj K. Jha:
Register-transfer level estimation techniques for switching activity and power consumption. ICCAD 1996: 158-165 - [c38]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
A design for testability technique for RTL circuits using control/data flow extraction. ICCAD 1996: 329-336 - [c37]Anand Raghunathan, Sujit Dey, Niraj K. Jha, Kazutoshi Wakabayashi:
Controller re-specification to minimize switching activity in controller/data path circuits. ISLPED 1996: 301-304 - [c36]J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard:
Hardware-Software Co-Design for Test: It's the Last Straw! VTS 1996: 506-507 - 1995
- [c35]Santhanam Srinivasan, Niraj K. Jha:
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems. EURO-DAC 1995: 334-339 - [c34]Anand Raghunathan, Niraj K. Jha:
An iterative improvement algorithm for low power data path synthesis. ICCAD 1995: 597-602 - [c33]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ICCD 1995: 173-179 - [c32]Santhanam Srinivasan, Niraj K. Jha:
Task Allocation for Safety and Reliability in Distributed Systems. ICPP (2) 1995: 206-213 - [c31]Anand Raghunathan, Niraj K. Jha:
An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation. ISCAS 1995: 1069-1073 - [c30]Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng:
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. VLSI Design 1995: 171-176 - 1994
- [j27]Steven W. Burns, Niraj K. Jha:
A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme. IEEE Trans. Computers 43(4): 490-495 (1994) - [j26]Sying-Jyan Wang, Niraj K. Jha:
Algorithm-Based Fault Tolerance for FFT Networks. IEEE Trans. Computers 43(7): 849-854 (1994) - [j25]Jennifer Rexford, Niraj K. Jha:
Partitioned Encoding Schemes for Algorithm-Based Fault Tolerance in Massively Parallel Systems. IEEE Trans. Parallel Distributed Syst. 5(6): 649-653 (1994) - [j24]Bapiraju Vinnakota, Niraj K. Jha:
Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. IEEE Trans. Parallel Distributed Syst. 5(10): 1099-1106 (1994) - [c29]Sandeep Bhatia, Niraj K. Jha:
Genesis: A Behavioral Synthesis System for Hierarchical Testability. EDAC-ETC-EUROASIC 1994: 272-276 - [c28]Sandeep Bhatia, Niraj K. Jha:
Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. ICCD 1994: 91-96 - [c27]Anand Raghunathan, Niraj K. Jha:
Behavioral Synthesis for low Power. ICCD 1994: 318-322 - [c26]Shalini Yajnik, Niraj K. Jha:
Synthesis of Fault Tolerant Architectures for Molecular Dynamics. ISCAS 1994: 247-250 - [c25]Shalini Yajnik, Niraj K. Jha:
Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor Systems. ISCAS 1994: 333-336 - 1993
- [j23]Niraj K. Jha:
Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers. IEEE Trans. Computers 42(2): 179-189 (1993) - [j22]Ramesh K. Sitaraman, Niraj K. Jha:
Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems. IEEE Trans. Computers 42(7): 780-793 (1993) - [j21]Bapiraju Vinnakota, Niraj K. Jha:
Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems. IEEE Trans. Computers 42(8): 924-937 (1993) - [j20]Niraj K. Jha, Abha Ahuja:
Easily testable nonrestoring and restoring gate-level cellular array dividers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 114-123 (1993) - [j19]Niraj K. Jha, Sying-Jyan Wang:
Design and synthesis of self-checking VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(6): 878-887 (1993) - [j18]Bapiraju Vinnakota, Niraj K. Jha:
Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs. IEEE Trans. Parallel Distributed Syst. 4(8): 864-874 (1993) - [c24]Tien-Chien Lee, Niraj K. Jha, Wayne H. Wolf:
Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments. DAC 1993: 292-297 - [c23]Sandeep Bhatia, Niraj K. Jha:
Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. ICCD 1993: 151-154 - [c22]Santhanam Srinivasan, Niraj K. Jha:
Efficient Diagnosis in Algorithm-Based Fault Tolerant Multiprocessor Systems. ICCD 1993: 592-595 - [c21]Shalini Yajnik, Niraj K. Jha:
Design of Algorithm-Based Fault Tolerant Systems With In-System Checks. ICPP (1) 1993: 246-253 - [c20]Tien-Chien Lee, Niraj K. Jha, Wayne H. Wolf:
A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths. ITC 1993: 744-753 - [c19]Sandeep Bhatia, Niraj K. Jha:
Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. VLSI Design 1993: 275-280 - 1992
- [c18]Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller:
Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. FTCS 1992: 280-287 - [c17]Tien-Chien Lee, Wayne H. Wolf, Niraj K. Jha:
Behavioral synthesis for easy testability in data path scheduling. ICCAD 1992: 616-619 - [c16]Tien-Chien Lee, Wayne H. Wolf, Niraj K. Jha, John M. Acken:
Behavioral Synthesis for Easy Testability in Data Path Allocation. ICCD 1992: 29-32 - [c15]Niraj K. Jha, Sying-Jyan Wang, Phillip C. Gripka:
Multiple Input Bridging Fault Detection in CMOS Sequential Circuits. ICCD 1992: 369-372 - [c14]Shalini Yajnik, Niraj K. Jha:
Design and Analysis of Fault-Detecting and Fault-Locating Schedules for Computation DAGs. IPPS 1992: 348-351 - [c13]Steven W. Burns, Niraj K. Jha:
A totally self-checking checker for a parallel unordered coding scheme. VTS 1992: 165-170 - 1991
- [j17]Qiao Tong, Niraj K. Jha:
Design of C-testable DCVS binary array dividers. IEEE J. Solid State Circuits 26(2): 134-141 (1991) - [j16]Niraj K. Jha, Qiao Tong:
Robustly testable static CMOS parity trees derived from binary decision diagrams. IEEE J. Solid State Circuits 26(11): 1728-1733 (1991) - [j15]Niraj K. Jha:
Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(1): 136-143 (1991) - [j14]Konstantinos I. Diamantaras, Niraj K. Jha:
A new transition count method for testing of logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(3): 407-410 (1991) - [j13]Andres R. Takach, Niraj K. Jha:
Easily testable gate-level and DCVS multipliers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(7): 932-942 (1991) - [j12]Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha:
Design of robustly testable combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 1036-1048 (1991) - [c12]Bapiraju Vinnakota, Niraj K. Jha:
MACHETE: synthesis of sequential machines for easy testability. EURO-DAC 1991: 289-293 - [c11]Bapiraju Vinnakota, Niraj K. Jha:
Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis. FTCS 1991: 504-511 - [c10]Niraj K. Jha, Sying-Jyan Wang:
Design and Synthesis of Self-Checking VLSI Circuits and Systems. ICCD 1991: 578-581 - [c9]Ramesh K. Sitaraman, Niraj K. Jha:
Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessors Systems. Fault-Tolerant Computing Systems 1991: 396-406 - 1990
- [j11]Niraj K. Jha:
Testing of differential cascode voltage switch one-count generators. IEEE J. Solid State Circuits 25(1): 246-253 (1990) - [j10]Niraj K. Jha, Qiao Tong:
Testing of multiple-output domino logic (MODL) CMOS circuits. IEEE J. Solid State Circuits 25(3): 800-805 (1990) - [j9]Qiao Tong, Niraj K. Jha:
Testing of zipper CMOS logic circuits. IEEE J. Solid State Circuits 25(3): 877-880 (1990) - [j8]Niraj K. Jha:
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 332-336 (1990) - [c8]Niraj K. Jha, Qiao Tong:
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring. EURO-DAC 1990: 350-354 - [c7]Bapiraju Vinnakota, Niraj K. Jha:
A dependence graph-based approach to the design of algorithm-based fault tolerant systems. FTCS 1990: 122-129 - [c6]Niraj K. Jha, Carol Q. Tong:
Design of robustly testable static CMOS parity trees derived from binary decision diagrams. ICCD 1990: 103-106
1980 – 1989
- 1989
- [j7]Niraj K. Jha:
Comments on 'A MOS implementation of totally self-checking checker for the 1-out-of-3 code'. IEEE J. Solid State Circuits 24(5): 1470-1471 (1989) - [j6]Niraj K. Jha:
Separable codes for detecting unidirectional errors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(5): 571-574 (1989) - [j5]Niraj K. Jha:
A totally self-checking checker for Borden's code. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(7): 731-736 (1989) - [c5]Niraj K. Jha:
Fault detection in CVS parity trees: application in SSC CVS parity and two-rail checkers. FTCS 1989: 407-414 - [c4]Niraj K. Jha:
Design of sufficiently strongly self-checking embedded checkers for systematic and separable codes. ICCD 1989: 120-123 - 1988
- [j4]Niraj K. Jha:
Multiple Stuck-Open Fault Detection in CMOS Logic Circuits. IEEE Trans. Computers 37(4): 426-432 (1988) - [j3]Niraj K. Jha:
Testing for multiple faults in domino-CMOS logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 109-116 (1988) - [j2]Gopal Gupta, Niraj K. Jha:
A universal test set for CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(5): 590-597 (1988) - [c3]Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha:
On the design of robust multiple fault testable CMOS combinational logic circuits. ICCAD 1988: 240-243 - [c2]Niraj K. Jha:
A new class of symmetric error correcting / unidirectional error detecting codes. ICCD 1988: 283-286 - 1986
- [c1]Niraj K. Jha:
Detecting Multiple Faults in CMOS Circuits. ITC 1986: 514-519 - 1985
- [j1]Niraj K. Jha, Jacob A. Abraham:
Design of Testable CMOS Logic Circuits Under Arbitrary Delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 264-269 (1985)
Coauthor Index
[i24] [j190] [j188] [j185] [j176] [j170] [j169] [c198] [j163] [j157] [j150] [j147] [c194] [c193] [c192] [c190] [j140] [j139] [j138] [j135] [c180] [c179] [c174] [j118] [c167] [j115] [j111] [j110] [j109] [j106] [j104] [j102] [j101] [j100] [j99] [c158] [j95] [j94] [j93] [j92] [j90] [j87] [j86] [c153] [c152] [c149] [c148] [c145] [c144] [c141] [j81] [j80] [j79] [c140] [c139] [c138] [c137] [c135] [c129] [c127] [j76] [j75] [j74] [j73] [j70] [c123] [c122] [c118] [c117] [c112] [c111] [j69] [j68] [j67] [c108] [c107] [c105] [c102] [c101] [c97] [c95] [p1] [j64] [c91] [c90] [c88] [c83] [c80] [c79] [j57] [j55] [c74] [j50] [j48] [j47] [j41] [c67] [b1] [j37] [c61] [c53] [c50] [j33] [j32] [c48] [c47] [c41] [c40] [c39] [c38] [c37] [c34] [c33] [c31] [c27]
[c161] [j115] [j111] [j110] [j109] [j106] [j104] [j102] [j101] [j100] [j99] [c158] [j96] [j95] [j94] [j93] [j92] [j90] [j87] [j86] [c153] [c152] [c149] [c148] [c145] [c144] [c141] [j80] [c140] [c139] [c138] [c137] [c135] [c129] [c127] [j75] [j74] [c122] [c118] [c117] [c112] [c108] [c102] [c101] [c99] [c97] [j65] [j63] [c91] [c90] [j60] [j59] [j58] [c76] [c75] [j53] [c71] [c70] [c65] [c63] [c54] [c51]
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