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ORCIDVijay Gangaram
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2010 – 2019
- 2018
[c12]I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram:
Online Scan Diagnosis : A Novel Approach to Volume Diagnosis. ITC 2018: 1-10- 2013
- [c11]Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram:
Test generation for circuits with embedded memories using SMT. ETS 2013: 1 - 2012
- [c10]Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram:
A Novel SMT-Based Technique for LFSR Reseeding. VLSI Design 2012: 394-399 - [c9]Sarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram:
A SMT-based diagnostic test generation method for combinational circuits. VTS 2012: 215-220 - 2011
- [c8]Sarvesh Prabhu, Michael S. Hsiao, Saparya Krishnamoorthy, Loganathan Lingappan, Vijay Gangaram, Jim Grundy:
An Efficient 2-Phase Strategy to Achieve High Branch Coverage. Asian Test Symposium 2011: 167-174
2000 – 2009
- 2009
- [j2]Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty:
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 697-708 (2009) - 2008
- [c7]Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram:
Efficient Selection of Observation Points for Functional Tests. ISQED 2008: 236-241 - 2007
- [c6]Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha:
Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits. VLSI Design 2007: 504-512 - [c5]Jian Kang, Sharad C. Seth, Vijay Gangaram:
Efficient RTL Coverage Metric for Functional Test Selection. VTS 2007: 318-324 - 2006
- [c4]Vijay Gangaram, Deepa Bhan, James K. Caldwell:
Functional Test Selection for High Volume Manufacturing. MTV 2006: 15-19 - [c3]Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram:
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. VTS 2006: 88-93
1990 – 1999
- 1998
- [j1]Sujit Dey, Vijay Gangaram, Miodrag Potkonjak:
A controller redesign technique to enhance testability of controller-data path circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 157-168 (1998) - 1997
- [c2]Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler:
Deriving Signal Constraints to Accelerate Sequential Test Generation. VLSI Design 1997: 488-494 - 1995
- [c1]Sujit Dey, Vijay Gangaram, Miodrag Potkonjak:
A controller-based design-for-testability technique for controller-data path circuits. ICCAD 1995: 534-540
Coauthor Index
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