"3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations."

Sourindra Chaudhuri, Niraj K. Jha (2014)

> Home

Details and statistics

DOI: 10.1145/2567670

access: closed

type: Journal Article

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jetc/ChaudhuriJ14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jetc/ChaudhuriJ14
Sourindra Chaudhuri, Niraj K. Jha:
3D vs. 2D Device Simulation of FinFET Logic Gates under PVT Variations. ACM J. Emerg. Technol. Comput. Syst. 10(3): 26:1-26:19 (2014)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.