"Design of Testable CMOS Logic Circuits Under Arbitrary Delays."

Niraj K. Jha, Jacob A. Abraham (1985)

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DOI: 10.1109/TCAD.1985.1270122

access: closed

type: Journal Article

metadata version: 2020-09-24

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Niraj K. Jha, Jacob A. Abraham:
Design of Testable CMOS Logic Circuits Under Arbitrary Delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 264-269 (1985)

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