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ORCIDSandeep Bhatia
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2020 – today
- 2023
[c16]Sandeep Bhatia
, R. V. S. Bhadauria, Komal Mehrotra, Jeevan Malik, Amit Kumar Goel, Bharat Bhusan Naib:
A Comparative Analysis and Design Criteria of MAC, SMAC, and TMAC Protocols in Wireless Sensor Network. ICCCNT 2023: 1-6- [c15]Karan Madan, Devraj Gautam, Sandeep Bhatia, Sidhant Kashyap, Chanchal, Priyanka:
LoRaWAN Enabled Wildland Safety Fire Alert System. ICCCNT 2023: 1-7 - 2021
- [j6]Naveen Kumar, Rahul Kaushik, Chandana Tennakoon, Vladimir N. Uversky, Sonia Longhi, Kam Y. J. Zhang, Sandeep Bhatia:
Insights into the evolutionary forces that shape the codon usage in the viral genome segments encoding intrinsically disordered protein regions. Briefings Bioinform. 22(5) (2021) - [c14]Parthasarathy Ranganathan, Daniel Stodolsky, Jeff Calow, Jeremy Dorfman, Marisabel Guevara, Clinton Wills Smullen IV, Aki Kuusela, Raghu Balasubramanian, Sandeep Bhatia, Prakash Chauhan, Anna Cheung, In Suk Chong, Niranjani Dasharathi, Jia Feng, Brian Fosco, Samuel Foss, Ben Gelb, Sara J. Gwin, Yoshiaki Hase, Da-ke He, C. Richard Ho, Roy W. Huffman Jr., Elisha Indupalli, Indira Jayaram, Poonacha Kongetira, Cho Mon Kyaw, Aaron Laursen, Yuan Li, Fong Lou, Kyle A. Lucke, J. P. Maaninen, Ramon Macias, Maire Mahony, David Alexander Munday, Srikanth Muroor, Narayana Penukonda, Eric Perkins-Argueta, Devin Persaud, Alex Ramírez, Ville-Mikko Rautio, Yolanda Ripley, Amir Salek, Sathish Sekar, Sergey N. Sokolov, Rob Springer, Don Stark, Mercedes Tan, Mark S. Wachsler, Andrew C. Walton, David A. Wickeraad, Alvin Wijaya, Hon Kwan Wu:
Warehouse-scale video acceleration: co-design and deployment in the wild. ASPLOS 2021: 600-615
2010 – 2019
- 2019
- [c13]Pulkit Agrawal, Rajat Arya, Aanchal Bindal, Sandeep Bhatia, Anupriya Gagneja, Joseph Godlewski, Yucheng Low, Timothy Muss, Mudit Manu Paliwal, Sethu Raman, Vishrut Shah, Bochao Shen, Laura Sugden, Kaiyu Zhao, Ming-Chuan Wu:
Data Platform for Machine Learning. SIGMOD Conference 2019: 1803-1816 - 2018
- [c12]Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, Erik Jan Marinissen:
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers. ETS 2018: 1-6 - 2015
- [j5]V. N. Muhasin Asaf, Amod Kumar, Ashwin Ashok Raut, Sandeep Bhatia, Anamika Mishra:
In-silico search of virus-specific host microRNAs regulating avian influenza virus NS1 expression. Theory Biosci. 134(1-2): 65-73 (2015) - 2010
- [j4]Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki:
Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression. IEICE Trans. Inf. Syst. 93-D(1): 17-23 (2010) - [c11]Sandeep Bhatia:
Low power compression architecture. VTS 2010: 183-187
2000 – 2009
- 2009
- [j3]Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller:
CTL and Its Usage in the EDA Industry. IEEE Des. Test Comput. 26(1): 36-43 (2009) - 2008
- [c10]Brion L. Keller, Sandeep Bhatia, Thomas Bartenstein, Brian Foutz, Anis Uzzaman:
Optimizing Test Data Volume Using Hybrid Compression. ATS 2008: 157-162 - [c9]Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam:
A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings. VLSI Design 2008: 187-193 - 2003
- [c8]Sandeep Bhatia:
Test Compaction by Using Linear-Matrix Driven Scan Chains. DFT 2003: 185-190
1990 – 1999
- 1998
- [j2]Sandeep Bhatia, Niraj K. Jha:
Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 608-619 (1998) - [c7]Prab Varma, Sandeep Bhatia:
A structured test re-use methodology for core-based system chips. ITC 1998: 294-302 - 1997
- [c6]Sandeep Bhatia, Prab Varma:
Test Compaction in a Parallel Access Scan Environment. Asian Test Symposium 1997: 300-305 - 1996
- [j1]Sandeep Bhatia, Niraj K. Jha:
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 228-243 (1996) - [c5]Sandeep Bhatia, Tushar Gheewala, Prab Varma:
A Unifying Methodology for Intellectual Property and Custom Logic Testing. ITC 1996: 639-648 - 1994
- [c4]Sandeep Bhatia, Niraj K. Jha:
Genesis: A Behavioral Synthesis System for Hierarchical Testability. EDAC-ETC-EUROASIC 1994: 272-276 - [c3]Sandeep Bhatia, Niraj K. Jha:
Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches. ICCD 1994: 91-96 - 1993
- [c2]Sandeep Bhatia, Niraj K. Jha:
Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan. ICCD 1993: 151-154 - [c1]Sandeep Bhatia, Niraj K. Jha:
Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. VLSI Design 1993: 275-280
Coauthor Index
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