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2020 – today
- 2024
[c26]Timothy O. Dickson, Zeynep Toprak Deniz, Martin Cochet, John F. Bulzacchelli, Marcel A. Kossel, Pier Andrea Francese, Thomas Morf, Jonathan E. Proesel, Herschel A. Ainspan, Matthias Brändli, Mounir Meghelli:
Digital-to-Analog Converters for 100+ Gb/s Wireline Transmitters: Architectures, Circuits, and Calibration. CICC 2024: 1-8- [c25]Zeynep Toprak Deniz, Timothy O. Dickson, Martin Cochet, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Matthias Brändli, Thomas Morf, Michael P. Beakes, Mounir Meghelli:
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. VLSI Technology and Circuits 2024: 1-2 - 2022
- [c24]Serdar S. Yonar, Pier Andrea Francese
, Matthias Brändli, Marcel A. Kossel, Thomas Morf, Jonathan E. Proesel, Sergey V. Rylov, Herschel A. Ainspan, Martin Cochet, Zeynep Toprak Deniz, Timothy O. Dickson, Troy J. Beukema, Christian W. Baks, Michael P. Beakes, John F. Bulzacchelli, Young-Ho Choi, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, Mounir Meghelli, Hyo-Gyuem Rhew, Daniel J. Friedman, Michael Choi, Mehmet Soyuer, Jongshin Shin:
An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. VLSI Technology and Circuits 2022: 168-169 - 2020
- [j25]Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli:
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. IEEE J. Solid State Circuits 55(1): 19-26 (2020) - [j24]Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli:
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". IEEE J. Solid State Circuits 55(4): 1124 (2020) - [j23]Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck, Mihai Sanduleanu, Xiaoxiong Gu, Christian W. Baks, Duixian Liu, Daniel J. Friedman:
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage. IEEE J. Solid State Circuits 55(6): 1516-1529 (2020) - [c23]Nicolas Dupuis, Jonathan E. Proesel, Nicolas Boyer, Herschel A. Ainspan, Christian W. Baks, Fuad E. Doany, Elaine Cyr, Benjamin G. Lee:
An 8×8 Silicon Photonic Switch Module with Nanosecond-Scale Reconfigurability. OFC 2020: 1-3 - [c22]Jonathan E. Proesel, Nicolas Dupuis, Herschel A. Ainspan, Christian W. Baks, Fuad E. Doany, Nicolas Boyer, Elaine Cyr, Benjamin G. Lee:
A Monolithically Integrated Silicon Photonics 8×8 Switch in 90nm SOI CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [c21]Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli:
A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS. ISSCC 2019: 122-124 - [c20]Daniel M. Kuchta, Jonathan E. Proesel, Fuad E. Doany, Wooram Lee, Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli, Petar K. Pepeljugoski, Xiaoxiong Gu, Michael P. Beakes, Mark Schultz, Marc Taubenblatt, Paul Fortier, Catherine Dufort, Éric Turcotte, Marc-Olivier Pion, Charles Bureau, Frank Flens, Greta Light, Blake Trekell, Kevin Koski:
Multi-Wavelength Optical Transceivers Integrated on Node (MOTION). OFC 2019: 1-3 - [c19]Benjamin G. Lee, Nicolas Dupuis, Fuad E. Doany, Laurent Schares, Nicolas Boyer, Nathalie Normand, Herschel A. Ainspan, Christian W. Baks, Jonathan E. Proesel, Isabel De Sousa, Mounir Meghelli, Marc A. Taubenblatt:
Toward Optical Networks using Rapid Amplified Multi-Wavelength Photonic Switches. OFC 2019: 1-3 - 2018
- [j22]Jonathan E. Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli:
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. IEEE J. Solid State Circuits 53(4): 1214-1226 (2018) - [c18]Benjamin G. Lee, Nicolas Dupuis, Jason Orcutt, Javier Ayala, Karen Nummy, Herschel A. Ainspan, Jonathan E. Proesel, Christian W. Baks, Douglas M. Gill, Mounir Meghelli, William M. J. Green:
FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS. OFC 2018: 1-3 - 2017
- [c17]Timothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli:
6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS. ISSCC 2017: 118-119 - 2016
- [j21]Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Michael P. Beakes, Mounir Meghelli, Daniel J. Friedman:
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration. IEEE J. Solid State Circuits 51(8): 1744-1755 (2016) - [c16]Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman:
10.8 A 12-to-26GHz fractional-N PLL with dual continuous tuning LC-D/VCOs. ISSCC 2016: 196-198 - 2015
- [j20]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman:
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE J. Solid State Circuits 50(8): 1917-1931 (2015) - [c15]Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman:
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. CICC 2015: 1-4 - [c14]Mark A. Ferriss, Bodhisatwa Sadhu, Alexander V. Rylyakov, Herschel A. Ainspan, Daniel J. Friedman:
10.9 A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. ISSCC 2015: 1-3 - [c13]Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan:
14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation. VLSIC 2015: 268- - 2014
- [j19]Mark A. Ferriss, Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Daniel J. Friedman:
A 28 GHz Hybrid PLL in 32 nm SOI CMOS. IEEE J. Solid State Circuits 49(4): 1027-1035 (2014) - [c12]Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha:
TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. CICC 2014: 1-4 - [c11]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander V. Rylyakov, Benjamin D. Parker, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman:
A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. CICC 2014: 1-4 - [c10]Franco Stellari, Peilin Song, Herschel A. Ainspan:
Functional block extraction for hardware security detection using time-integrated and time-resolved emission measurements. VTS 2014: 1-6 - 2012
- [j18]Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman:
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. IEEE J. Solid State Circuits 47(4): 884-896 (2012) - [j17]John F. Bulzacchelli, Christian Menolfi, Troy J. Beukema, Daniel W. Storaska, Juergen Hertle, David Hanson, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, L. R. Chieco, Glenn Ritter, J. A. Sorice, Jon Garlett, Robert Callan, Matthias Braendli, Peter Buchmann, Marcel A. Kossel, Thomas Toifl, Daniel J. Friedman:
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. IEEE J. Solid State Circuits 47(12): 3232-3248 (2012) - [c9]John F. Bulzacchelli, Troy J. Beukema, Daniel W. Storaska, Ping-Hsuan Hsieh, Sergey V. Rylov, Daniel Furrer, Daniele Gardellini, Andrea Prati, Christian Menolfi, David Hanson, Juergen Hertle, Thomas Morf, Vivek Sharma, Ram Kelkar, Herschel A. Ainspan, William R. Kelly, Glenn Ritter, Jon Garlett, Robert Callan, Thomas Toifl, Daniel J. Friedman:
A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. ISSCC 2012: 324-326
2000 – 2009
- 2009
- [c8]Alexander V. Rylyakov, José A. Tierno, Herschel A. Ainspan, Jean-Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak Deniz, Daniel J. Friedman:
Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications. ISSCC 2009: 94-95 - [c7]John F. Bulzacchelli, Timothy O. Dickson, Zeynep Toprak Deniz, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Sergey V. Rylov, Daniel J. Friedman:
A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. ISSCC 2009: 368-369 - 2008
- [j16]Woogeun Rhee, Keith A. Jenkins, John C. Liobe, Herschel A. Ainspan:
Experimental Analysis of Substrate Noise Effect on PLL Performance. IEEE Trans. Circuits Syst. II Express Briefs 55-II(7): 638-642 (2008) - [c6]Alexander V. Rylyakov, José A. Tierno, Didem Zeliha Turker, Jean-Olivier Plouchart, Herschel A. Ainspan, Daniel J. Friedman:
A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS. ISSCC 2008: 516-517 - 2007
- [j15]Babak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget:
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback. IEEE J. Solid State Circuits 42(8): 1635-1641 (2007) - 2006
- [j14]John F. Bulzacchelli, Mounir Meghelli, Sergey V. Rylov, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, Lei Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman:
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. IEEE J. Solid State Circuits 41(12): 2885-2900 (2006) - [c5]Baharak Soltanian, Herschel A. Ainspan, Woogeun Rhee, Daniel J. Friedman, Peter R. Kinget:
An Ultra Compact Differentially Tuned 6 GHz CMOS LC VCO with Dynamic Common-Mode Feedback. CICC 2006: 671-674 - [c4]Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman:
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. ISSCC 2006: 213-222 - 2005
- [j13]Troy J. Beukema, Michael Sorna, Karl Selander, Steven Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes:
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization. IEEE J. Solid State Circuits 40(12): 2633-2645 (2005) - 2003
- [j12]Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer:
SiGe BiCMOS integrated circuits for high-speed serial communication links. IBM J. Res. Dev. 47(2-3): 259-282 (2003) - [j11]Scott K. Reynolds, Brian A. Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. Ainspan:
A direct-conversion receiver integrated circuit for WCDMA mobile systems. IBM J. Res. Dev. 47(2-3): 337-354 (2003) - [j10]Scott K. Reynolds, Brian A. Floyd, Troy J. Beukema, Thomas Zwick, Ullrich R. Pfeiffer, Herschel A. Ainspan:
A direct-conversion receiver IC for WCDMA mobile systems. IEEE J. Solid State Circuits 38(9): 1555-1560 (2003) - [c3]Woogeun Rhee, Herschel A. Ainspan, Sergey V. Rylov, Alexander V. Rylyakov, Michael P. Beakes, Daniel J. Friedman, Sudhir M. Gowda, Mehmet Soyuer:
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. CICC 2003: 81-84 - 2000
- [j9]Mounir Meghelli, Benjamin D. Parker, Herschel A. Ainspan, Mehmet Soyuer:
SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems. IEEE J. Solid State Circuits 35(12): 1992-1995 (2000) - [j8]Mehmet Soyuer, Herschel A. Ainspan, Mounir Meghelli, Jean-Olivier Plouchart:
Low-power multi-GHz and multi-Gb/s SiGe BiCMOS circuits. Proc. IEEE 88(10): 1572-1582 (2000)
1990 – 1999
- 1999
- [c2]Jean-Olivier Plouchart, Herschel A. Ainspan, Mehmet Soyuer:
A 5.2 GHz 3.3 V I/Q SiGe RF transceiver. CICC 1999: 217-220 - 1998
- [j7]Joachim N. Burghartz, Daniel C. Edelstein, Mehmet Soyuer, Herschel A. Ainspan, Keith A. Jenkins:
RF circuit design aspects of spiral inductors on silicon. IEEE J. Solid State Circuits 33(12): 2028-2034 (1998) - [j6]Jungwook Yang, Joongho Choi, Daniel M. Kuchta, Kevin G. Stawiasz, Petar K. Pepeljugoski, Herschel A. Ainspan:
A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology. IEEE J. Solid State Circuits 33(12): 2197-2204 (1998) - 1997
- [j5]Mehmet Soyuer, Joachim N. Burghartz, Herschel A. Ainspan, Keith A. Jenkins, Peter Xiao, Arvin R. Shahani, Margaret S. Dolan, David L. Harame:
An 11 GHz 3-V SiGe voltage controlled oscillator with integrated resonator. IEEE J. Solid State Circuits 32(9): 1451-1454 (1997) - 1996
- [j4]Mehmet Soyuer, Keith A. Jenkins, Joachim N. Burghartz, Herschel A. Ainspan, Frank J. Canora, Slaila Ponnapalli, John F. Ewen, William E. Pence:
A 2.4-GHz silicon bipolar oscillator with integrated resonator. IEEE J. Solid State Circuits 31(2): 268-270 (1996) - [j3]Albert X. Widmer, Kevin R. Wrenner, Herschel A. Ainspan, Ben Parker, Pierre Austruy, Bernard Brezzo, Anne-Marie Haen, John F. Ewen, Mehmet Soyuer, Alain Blanc, Jean-Claude Abbiate, Alina Deutsch, Hyun J. Shin:
Single-chip 4×500-MBd CMOS transceiver. IEEE J. Solid State Circuits 31(12): 2004-2014 (1996) - 1995
- [j2]Daniel M. Kuchta, Herschel A. Ainspan, Frank J. Canora, Richard P. Schneider Jr.:
Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier. IBM J. Res. Dev. 39(1-2): 63-72 (1995) - [j1]John F. Ewen, Mehmet Soyuer, Albert X. Widmer, Kevin R. Wrenner, Benjamin D. Parker, Herschel A. Ainspan:
CMOS circuits for Gb/s serial data communication. IBM J. Res. Dev. 39(1-2): 73-82 (1995) - [c1]Mehmet Soyuer, Herschel A. Ainspan, John F. Ewen:
A 1.6-Gb/s CMOS Phase-Frequency Locked Loop for Timing Recovery. ISCAS 1995: 187-190
Coauthor Index
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