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ORCIDCornelia K. Tsang
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2010 – 2019
- 2012
[j7]Timothy O. Dickson, Yong Liu, Sergey V. Rylov
, Bing Dang, Cornelia K. Tsang, Paul S. Andry, John F. Bulzacchelli, Herschel A. Ainspan, Xiaoxiong Gu, Lavanya Turlapati, Michael P. Beakes, Benjamin D. Parker, John U. Knickerbocker, Daniel J. Friedman:
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. IEEE J. Solid State Circuits 47(4): 884-896 (2012)
2000 – 2009
- 2008
- [j6]John U. Knickerbocker, Paul S. Andry, Bing Dang, Raymond R. Horton, Mario J. Interrante, Chirag S. Patel, Robert J. Polastre, Katsuyuki Sakuma, Ranjani Sirdeshmukh, Edmund J. Sprogis, Sri M. Sri-Jayantha, Antonio M. Stephens, Anna W. Topol, Cornelia K. Tsang, Bucknell C. Webb, Steven L. Wright:
Three-dimensional silicon integration. IBM J. Res. Dev. 52(6): 553-569 (2008) - [j5]Paul S. Andry, Cornelia K. Tsang, Bucknell C. Webb, Edmund J. Sprogis, Steven L. Wright, Bing Dang, Dennis G. Manzer:
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications. IBM J. Res. Dev. 52(6): 571-581 (2008) - [j4]Bing Dang, Steven L. Wright, Paul S. Andry, Edmund J. Sprogis, Cornelia K. Tsang, M. John Interrante, Bucknell C. Webb, Robert J. Polastre, Raymond R. Horton, Chirag S. Patel, Arun Sharma, J. Zheng, Katsuyuki Sakuma, John U. Knickerbocker:
3D chip stacking with C4 technology. IBM J. Res. Dev. 52(6): 599-609 (2008) - [j3]Katsuyuki Sakuma, Paul S. Andry, Cornelia K. Tsang, Steven L. Wright, Bing Dang, Chirag S. Patel, Bucknell C. Webb, J. Maria, Edmund J. Sprogis, S. K. Kang, Robert J. Polastre, Raymond R. Horton, John U. Knickerbocker:
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. IBM J. Res. Dev. 52(6): 611-622 (2008) - 2006
- [j2]John U. Knickerbocker, Chirag S. Patel, Paul S. Andry, Cornelia K. Tsang, L. Paivikki Buchwalter, Edmund J. Sprogis, Hua Gan, Raymond R. Horton, Robert J. Polastre, Steven L. Wright, John M. Cotte:
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias. IEEE J. Solid State Circuits 41(8): 1718-1725 (2006) - 2005
- [j1]John U. Knickerbocker, Paul S. Andry, L. Paivikki Buchwalter, Alina Deutsch, Raymond R. Horton, Keith A. Jenkins, Young Hoon Kwark, Gerald McVicker, Chirag S. Patel, Robert J. Polastre, Christian D. Schuster, Arun Sharma, Sri M. Sri-Jayantha, Christopher W. Surovic, Cornelia K. Tsang, Bucknell C. Webb, Steven L. Wright, Samuel R. McKnight, Edmund J. Sprogis, Bing Dang:
Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection. IBM J. Res. Dev. 49(4-5): 725-754 (2005) - [c1]John U. Knickerbocker, Chirag S. Patel, Paul S. Andry, Cornelia K. Tsang, L. Paivikki Buchwalter, Edmund J. Sprogis, Hua Gan, Raymond R. Horton, Robert J. Polastre, Steven L. Wright, Christian D. Schuster, Christian W. Baks, Fuad E. Doany, Joanna Rosner, Steven Cordes:
Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology. CICC 2005: 659-662
Coauthor Index
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