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ORCIDIEEE Journal of Solid-State Circuits, Volume 26
Volume 26, Number 1, January 1991
- Anton Stölzle, Shankar Narayanaswamy, Hy Murveit, Jan M. Rabaey, Robert W. Brodersen:
Integrated circuits for a real-time large-vocabulary continuous speech recognition system. 2-11 - Masashi Horiguchi, Jun Etoh, Masakazu Aoki, Kiyoo Itoh, Tetsuro Matsumoto:
A flexible redundancy technique for high-density DRAMs. 12-17 - Michel S. J. Steyaert, Wout Bijker, Pieter Vorenkamp, Jan Sevenhans:
ECL-CMOS and CMOS-ECL interface in 1.2- mu m CMOS for 150-MHz digital ECL data transmission systems. 18-24 - Minoru Fujishima, Kunihiro Asada, Takuo Sugano:
Evaluation of delay-time degradation of low-voltage BiCMOS based on a novel analytical delay-time modeling. 25-31 - Sanjay Dhar, Mark A. Franklin:
Optimum buffer circuits for driving long uniform lines. 32-40 - Germano Nicollini, Daniel Senderowicz:
A CMOS bandgap reference for differential signal processing. 41-50 - Tomohisa Wada, Masanao Eino, Motomu Ukita, Kenji Anami:
Variable bit organization as a new test function for standard memories. 51-54 - Chin-Long Wey, Tsin-Yuan Chang, Jyhyeuan Ding:
Design of fault-diagnosable and repairable folded PLAs for yield enhancement. 54-57 - Anura P. Jayasumana, Yashwant K. Malaiya, Rochit Rajsuman:
Design of CMOS circuits for stuck-open fault testability. 58-61 - Jih-Shyr Yih, Pinaki Mazumder:
Circuit behavior modeling and compact testing performance evaluation. 62-66 - Kuok-Young Ling, Peter M. Van Peteghem, Sang-Yong Lee, Hain-Ching Liu, Hector Sanchez:
A rad-hard, low-noise, high-speed, BiFET charge preamplifier for warm liquid calorimetry in the SSC. 66-69 - David E. Fulkerson:
Feedback FET logic: a robust, high-speed low-power GaAs logic family. 70-74 - Kazutoshi Nakajima, Hirofumi Kan, Yoshihiko Mizushima:
Power-speed product of an optical flip-flop memory with optical feedback. 75-76 - Thomas C. Banwell:
Performance limitations of low-voltage regulators using only n-p-n transistors. 77-80
Volume 26, Number 2, February 1991
- Jens Sparsø, Henrik N. Jorgensen, Erik Paaske, Steen Pedersen, Thomas Rubner-Petersen:
An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures. 90-97 - Johannes M. Mulder, Nhon T. Quach, Michael J. Flynn:
An area model for on-chip memories and its application. 98-106 - Alfredo R. Linz:
A low-power PLA for a signal processor. 107-115 - Shyoichi Miyazawa, Ryutaro Horita, Kenichi Hase, Kazuo Kato, Shinichi Kojima:
A BiCMOS PLL-based data separator circuit with high stability and accuracy. 116-121 - Takayasu Sakurai, A. Richard Newton:
Delay analysis of series-connected MOSFET circuits. 122-131 - Linda M. Geppert, Urs Bapst, David F. Heidel, Keith A. Jenkins:
Ion microbeam probing of sense amplifiers to analyze single event upsets in a CMOS DRAM. 132-134 - Qiao Tong, Niraj K. Jha:
Design of C-testable DCVS binary array dividers. 134-141 - Feng Kuo, Huan Dang, Stephen R. Whiteley, Masoud Radparvar:
A superconducting tracking A/D converter. 142-145 - Tai-Haur Kuo, Hung Chang Lin, Robert C. Potter, Dave Shupe:
A novel A/D converter using resonant tunneling diodes. 145-149 - Sherif H. K. Embabi, Abdellatif Bellaouar, Mohamed I. Elmasry, Robert A. Hadaway:
New full-voltage-swing BiCMOS buffers. 150-153 - Meng-Kai Chen:
The importance of the non-quasi-static bipolar transistor model for circuit applications. 153-160 - Bernabé Linares-Barranco, Ángel Rodríguez-Vázquez, Edgar Sánchez-Sinencio, José L. Huertas:
CMOS OTA-C high-frequency sinusoidal oscillators. 160-165 - Mel Bazes:
Two novel fully complementary self-biased CMOS differential amplifiers. 165-168
Volume 26, Number 3, March 1991
- Vittorio Comino, Michel S. J. Steyaert, Gabor C. Temes:
A first-order current-steering sigma-delta modulator. 176-183 - Andrew Gruss, L. Richard Carley, Takeo Kanade:
Integrated sensor and range-finding analog signal processor. 184-191 - Terri S. Fiez, Guojin Liang, David J. Allstot:
Switched-current circuit design issues. 192-202 - Andrew N. Karanicolas, Kenneth K. O, John Y. A. Wang, Hae-Seung Lee, Rafael L. Reif:
A high-frequency fully differential BiCMOS operational amplifier. 203-208 - Serge Maginot, Freddy Balestro, Christophe Joanblanq, Patrice Senn, Jacques Palico:
A general-purpose high-speed equalizer. 209-216 - Jud Leonard, Neil Weste, Lawrence Bodony, Stephen Harston, Richard Meaney:
A 66-MHz DSP-augmented RAMDAC for smooth-shaded graphic applications. 217-228 - J. A. K. S. Jayasinghe, F. Moelaert El-Hadidy, Georgios Karagiannis, Otto E. Herrmann, Jos Smit:
Two-level pipelined systolic array graphics engine. 229-236 - Imran Shah, Olu Akiwumi-Assani, Brian Johnson:
A chip set for lossless image compression. 237-244 - Russell S. Hinds, Shelly R. Canaga, Gary M. Lee, Ashish K. Choudhury:
A 20 K GaAs array with 10 K of embedded SRAM. 245-256 - Anthony J. McAuley, Charles J. Cotton:
A self-testing reconfigurable CAM. 257-261 - Bertrand Hochet, Vincent Peiris, Samer Abdo, Michel J. Declercq:
Implementation of a learning Kohonen neuron based on a new multilevel storage technique. 262-267 - Lloyd W. Massengill:
A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation. 268-276 - Jonathan Rose, Stephen Brown:
Flexibility of interconnection structures for field-programmable gate arrays. 277-282 - Genhong Ruan:
A behavioral model of A/D converters using a mixed-mode simulator. 283-290 - Tamal Mukherjee, L. Richard Carley:
Rapid yield estimation as a computer aid for analog circuit design. 291-299 - Jeannie H. Panner, Richard P. Abato, Robert W. Bassett, Keith M. Carrig, Pamela S. Gillis, David J. Hathaway, Terrence W. Sehr:
A comprehensive CAD system for high-performance 300 K-circuit ASIC logic chips. 300-309 - Klaus Milzner, Werner Brockherde:
SILAS: a knowledge-based simulation assistant. 310-318 - Hong You, Mani Soma:
Crosstalk and transient analyses of high-speed interconnects and packages. 319-329 - John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley:
KOAN/ANAGRAM II: new tools for device-level analog placement and routing. 330-342 - Hirofumi Shinohara, Noriaki Matsumoto, Kumiko Fujimori, Yoshiki Tsujihashi, Hiroomi Nakao, Shuichi Kato, Yasutaka Horiba, Akiharu Tada:
A flexible multiport RAM compiler for data path. 343-349 - Sujit Dey, Franc Brglez, Gershon Kedem:
Circuit partitioning for logic synthesis. 350-363 - Sheng-Fu Wu, P. David Fisher:
Automating the design of asynchronous sequential logic circuits. 364-370 - Christian Piguet:
Logic synthesis of race-free asynchronous CMOS circuits. 371-380 - Kimiyoshi Usami, Yukio Sugeno, Nobu Matsumoto, Shojiro Mori:
Hierarchical symbolic design methodology for large-scale data paths. 381-385 - Stacy W. Mehranfar:
A technology-independent approach to custom analog cell generation. 386-393 - Ton Kostelijk, Bart De Loore:
Automatic verification of library-based IC designs. 394-403 - Michael A. Lucente, Clifford H. Harris, Robert M. Muir:
Memory system reliability improvement through associative cache redundancy. 404-409 - Paul G. Y. Tsui, Peter M. Lee, Frank K. Baker, James D. Hayden, Lee Howington, Tom Tiwald, Brian Mowry:
A circuit level hot-carrier evaluation system. 410-414 - Joseph F. Jensen, William E. Stanchina, Robert A. Metzger, David B. Rensch, Ross F. Lohr, Renee Wong Quen, Michael W. Pierce, Young K. Allen, Peggy F. Lou:
AlInAs/GaInAs HBT IC technology. 415-421 - Ali A. Iranmanesh, Vida Ilderem, Madan Biswal, Bami Bastani:
A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications. 422-426 - Toshiaki Hanibuchi, Masahiro Ueda, Keiichi Higashitani, Masahiro Hatanaka, Koichiro Mashiko, Akiharu Tada:
A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates. 427-431 - Robert P. Masleid:
High-density central I/O circuits for CMOS. 431-435 - Erik De Man, Michael Schulz, W. Haberecht:
A digital interpolation filter chip with 32 programmable coefficients for 80 MHz sampling frequency. 435-439 - Takashi Akioka, Atsushi Hiraishi, Tatsumi Yamauchi, Yuji Yokoyama, Shigeru Takahashi, Masahiro Iwamura, Yutaka Kobayashi, Akira Ide, Nobuyuki Gotou, Kazunori Onozawa, Hideaki Uchida:
A 6-ns 256-kb BiCMOS TTL SRAM. 439-443 - Dennis C. Chen, R. Yu, Jan M. Rabaey, Robert W. Brodersen:
A VLSI grammar processing subsystem for a real-time large-vocabulary continuous speech recognition system. 443-448 - K. Ramachandran, R. R. Cordell, D. F. Daly, D. N. Deutsch, A. F. Kwan:
SYMCELL-a symbolic standard cell system. 449-452 - Wen-Jay Hsu, Bing J. Sheu, Sudhir M. Gowda:
Design of reliable VLSI circuits using simulation techniques. 452-457
Volume 26, Number 4, April 1991
- Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh:
An experimental 1.5-V 64-Mb DRAM. 465-472 - Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima:
A divided/shared bit-line sensing scheme for ULSI DRAM cores. 473-478 - Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama, Tohru Furuyama:
A 12 MHz data cycle 4 Mb DRAM with pipeline operation. 479-483 - Mike McConnell, Buster Ashmore, Rick Bussey, Manzur Gill, Sung-Wei Lin, Dave McElroy, John F. Schreck, Pradeep Shah, Harvey Stiegler, Phat Truong, Agerico L. Esquivel, Jim Paterson, Bert Riemenschneider:
An experimental 4 Mb flash EEPROM with sector erase. 484-491 - Masaki Momodomi, Tomoharu Tanaka, Yoshihisa Iwata, Yoshiyuki Tanaka, Hideko Oodaira, Yasuo Itoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka:
A 4 Mb NAND EEPROM with tight programmed V/sub t/ distribution. 492-496 - Takaaki Nozaki, Toshiaki Tanaka, Yoshiro Kijiya, Eita Kinoshita, Tatsuo Tsuchiya, Yutaka Hayashi:
A 1 Mb EEPROM with MONOS memory cell for semiconductor disk application. 497-501 - Hirotada Kuriyama, Toshihiko Hirose, Shuji Murakami, Tomohisa Wada, Kore-aki Fujita, Yasumasa Nishimura, Kenji Anami:
An 8 ns 4 Mb serial access memory. 502-506 - Atsushi Ohba, Shigeki Ohbayashi, Toru Shiomi, Satoshi Takano, Kenji Anami, Hiroki Honda, Yoshiyuki Ishigaki, Masahiro Hatanaka, Shigeo Nagao, Shimpei Kayano:
A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy. 507-512 - Takakuni Douseki, Yasuo Ohmori, Hideo Yoshino, Junzo Yamada:
Fast-access BiCMOS SRAM architecture with a V/sub SS/ generator. 513-517 - Yasunobu Nakase, Kakutaro Suda, Koichiro Mashiko, Tatsuhiko Ikeda, Shinpei Kayano:
A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing. 518-524 - Evert Seevinck, Petrus J. van Beers, Hans Ontrop:
Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's. 525-536 - Frederick P. Herrmann, Craig L. Keast, Keisuke Ishio, Jon P. Wade, Charles G. Sodini:
A dynamic three-state memory cell for high-density associative processors. 537-541 - Travis N. Blalock, Richard C. Jaeger:
A high-speed clamped bit-line current-mode sense amplifier. 542-548 - Ken-ichi Endo, Tsuneo Matsumura, Junzo Yamada:
Pipelined, time-sharing access technique for an integrated multiport memory. 549-554 - Mayu Miyauchi, Hiroaki Ikeda, Akira Tsujimoto, Yoshinori Sato, Junji Tajima, Takao Adachi, Kunihiro Hamaguchi, Naohiro Fukuhara:
100-MHz serial access architecture for 4-Mb field memory. 555-559 - Kazutami Arimoto, Mikio Asakura, Hideto Hidaka, Yoshio Matsuda, Kazuyasu Fujishima:
A circuit design of intelligent cache DRAM with automatic write-back capability. 560-565 - Kunio Uchiyama, Hirokazu Aoki, Osamu Nishii, Susumu Hatano, Osamu Nagashima, Kanji Oishi, Jun Kitano:
Design of a second-level cache chip for shared-bus multimicroprocessor systems. 566-571 - Itaru Kurosawa, Hiroshi Nakagawa, Masahiro Aoyagi, Shin Kosaka, Susumu Takada:
A fully operational 1 kb variable threshold Josephson RAM. 572-577 - Hyun J. Shin:
Full-swing BiCMOS logic circuits with complementary emitter-follower driver configuration. 578-584 - Kozaburo Kurita, Takashi Hotta, Tetsuo Nakano, Nobuaki Kitamura:
PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor. 585-589 - Fang-shi Lai:
A 10 ns hybrid number system data execution unit for digital signal processing systems. 590-599 - Junji Mori, Masato Nagamatsu, Masashi Hirano, Shigeru Tanaka, Makoto Noda, Yoshiaki Toyoshima, Kazuhiro Hashimoto, Hiroyuki Hayashida, Kenji Maeguchi:
A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology. 600-606 - Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Harufusa Kondoh, Shimpei Kayano:
A self-learning neural network chip with 125 neurons and 10 K self-organization synapses. 607-611 - Seigo Kotani, Atsuki Inoue, Shinya Hasuo:
Josephson macrocell array. 612-617 - Brian P. Brandt, Drew E. Wingard, Bruce A. Wooley:
Second-order sigma-delta modulation for digital-audio signal acquisition. 618-627 - Yuh-Min Lin, Beomsup Kim, Paul R. Gray:
A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS. 628-636 - Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh, Nobuharu Yazawa:
A 10-b 70-MS/s CMOS D/A converter. 637-642 - Peter J. Lim, Bruce A. Wooley:
A high-speed sample-and-hold technique using a Miller hold capacitance. 643-651 - Yoshiyuki Matsunaga, Hirofumi Yamashita, Shinji Ohsawa:
A highly sensitive on-chip charge detector for CCD area image sensor. 652-656 - David D. Lee, Randy H. Katz:
Using cache mechanisms to exploit nonrefreshing DRAMs for on-chip memories. 657-661 - Ching-Te Chuang:
NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit. 661-665 - Gerard Boudon, Pierre Mollier, Ieng Ong, Jean-Paul Nuez, Daniel Mauchauffee, Dominique Plassat, Jean-Louis Simonet, Frank Wallart:
Multiemitter BiCMOS logic circuit family. 665-669 - Shigetaka Takagi, Hajime Nitta, Jorge Koyama, Makoto Furihata, Nobuo Fujii, Minoru Nagata, Takeshi Yanagisawa:
100-MHz monolithic low-pass filters with transmission zeros using NIC integrators. 669-671 - Keith A. Jenkins, Walter H. Henkels:
Internal node probing of a DRAM with a low-temperature e-beam tester. 672-675 - Sherif H. K. Embabi, Abdellatif Bellaouar, Mohamed I. Elmasry:
Analysis and optimization of BiCMOS digital circuit structures. 676-679 - Hyun J. Shin, Pong-Fei Lu, Ching-Te Chuang:
A high-speed low-power JFET pull-down ECL circuit. 679-683 - Eric R. Fossum, Sabrina E. Kemeny, Richard A. Bredthauer, Mark LaShell:
Digitally programmable gain control circuit for charge-domain signal processing. 683-686
Volume 26, Number 5, May 1991
- Steven E. Butner, Scott L. Bordelon, Lisa Endres, James Dodd, Joy Shetler:
A fault-tolerant GaAs/CMOS interconnection network for scalable multiprocessors. 692-705 - Yen-Chuen Wei, Chung-Kuan Cheng, Ze'ev Wurman:
Multiple-level partitioning: an application to the very large-scale hardware simulator. 706-716 - Ming-Feng Chang, W. Kent Fuchs:
Loop-based design and reconfiguration of wafer-scale linear arrays with high harvest rates. 717-726 - Lionel J. D'Luna, Kenneth A. Parulski:
A systems approach to custom VLSI for a digital color imaging system. 727-737 - Haruo Kobayashi, Joseph L. White, Asad A. Abidi:
An active resistor network for Gaussian filtering of images. 738-748 - Hans J. Greub, John F. McDonald, Ted Creedon, Tadanori Yamaguchi:
High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic. 749-762 - Oyekunle A. Olukotun, Richard B. Brown, Ronald J. Lomax, Trevor N. Mudge, Karem A. Sakallah:
Multilevel optimization in the design of a high-performance GaAs microcomputer. 763-767 - Brian Von Herzen:
VLSI partitioning of a 2-Gs/s digital spectrometer. 768-772 - John Lazzaro:
A silicon model of an auditory neural representation of spectral shape. 772-777 - Ajai Jain, Babu Mandava, Janusz Rajski, Nicholas C. Rumin:
A fault-tolerant array processor designed for testability and self-reconfiguration. 778-788 - Denis Deschacht, Michel Robert, Daniel Auvergne:
Synchronous-mode evaluation of delays in CMOS structures. 789-795 - Naresh R. Shanbhag, Raymond E. Siferd:
A single-chip pipelined 2-D FIR filter using residue arithmetic. 796-805 - Tai-ichi Otsuji, Naoaki Narumi:
A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array. 806-811 - Ching-Te Chuang, Kenneth Chin:
High-speed low-power charge-buffered active-pull-down ECI circuit. 812-815 - Alain Fabre, Mustapha Alami:
Two bandpass active filters with reduced sensitivities. 816-819
Volume 26, Number 7, July 1991
- Peter J. A. Naus, Eise Carel Dijkmans:
Multibit oversampled Sigma Delta A/D converters as front end for CD players. 905-909 - Hans A. Leopold, Gunter Winkler, Paul O'Leary, Karl Ilzer, Jürgen Jernej:
A monolithic CMOS 20-b analog-to-digital converter. 910-916 - Cornelius A. A. Bastiaansen, D. Wouter J. Groeneveld, Hans J. Schouwenaars, Henk A. H. Termeer:
A 10-b 40-MHz 0.8- mu m CMOS current-output D/A converter. 917-921 - Jaap van der Plas:
MOSFET-C filter, with low excess noise and accurate automatic tuning. 922-929 - Rinaldo Castello, Luciano Tomasini:
1.5-V high-performance SC filters in BiCMOS technology. 930-936 - Hiroshi Tanimoto, Mikio Koyama, Yoshihiro Yoshida:
Realization of a 1-V active filter using a linearization technique employing plurality of emitter-coupled pairs. 937-945 - Jose Silva-Martinez, Michel S. J. Steyaert, Willy M. C. Sansen:
A large-signal very low-distortion transconductor for high-frequency continuous-time filters. 946-955 - Bernabé Linares-Barranco, Edgar Sánchez-Sinencio, Ángel Rodríguez-Vázquez, José L. Huertas:
A CMOS implementation of FitzHugh-Nagumo neuron model. 956-965 - Kurosh Madani, Patrick Garda, Eric Belhaire, Francis Devos:
Two analog counters for neural network implementation. 966-974 - Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Riedmüller, Karin Schmidt, Michael Weber:
A novel ASIC design approach based on a new machine paradigm. 975-989 - Andreas Curiger, Heinz Bonnenberg, Hubert Kaeslin:
Regular VLSI architectures for multiplication modulo (2/sup n/+1). 990-994 - Nans-Otto Leilich, Michael Dolle:
The latch bus driver system. 995-1002 - Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki:
Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. 1003-1010 - Karel Adriaensen, Leon Cloetens, Didier Gonze:
Advanced architecture for a one-chip 16*16 digital switch. 1011-1014 - Franz Dielacher, Jörg Hauptmann, Jochen Reisinger, Reinhard Steiner, Herbert Zojer:
A software programmable CMOS telephone circuit. 1015-1026 - Rolf Becker, Jaap Mulder:
SIGFRED: a low-power DTMF and signaling frequency detector. 1027-1037 - Didier Haspeslagh, Jan Sevenhans, Ann Delarbre, Lajos Kiss, Eric Moerman:
A four-channel digital signal processor in 1.2- mu m CMOS with on-chip D/A and A/D conversion serving four speech channels in a new-generation subscriber line circuit. 1038-1046 - Freddy Balestro, Alain Chianale, Gilles Privat, Mohamed Sameh Tawfik, Ivo Vandeweerd, Alain Wittmann:
Design of digital filters for advanced telecommunications ASIC's using a special-purpose silicon compiler. 1047-1055 - Albrecht P. Ströle, Hans-Joachim Wunderlich:
TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control. 1056-1063 - José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira:
Physical design of testable CMOS digital integrated circuits. 1064-1072 - Jean-Michel Fournier, Patrice Senn:
A 130-MHz 8-b CMOS video DAC for HDTV applications. 1073-1077 - Uwe Schoeneberg, Bedrich J. Hosticka, Frank V. Schnatz:
A CMOS readout amplifier for instrumentation applications. 1077-1080
Volume 26, Number 8, August 1991
- Robert J. Widlar:
Controlling substrate currents in junction-isolated ICs. 1090-1097 - Evert Seevinck, Remco J. Wiegerink:
Generalized translinear circuit principle. 1098-1102 - Peter Real, David H. Robertson, Christopher Wood Mangelsdorf, Theodore L. Tewksbury:
A wide-band 10-b 20 Ms/s pipelined ADC using current-mode signals. 1103-1109 - Andre H. Sayles, John P. Uyemura:
An optoelectronic CMOS memory circuit for parallel detection and storage of optical data. 1110-1115 - Mikio Kyomasu:
A new MOS imager using photodiode as current source. 1116-1122 - Yuji Hatano, Hideyuki Nagaishi, Shinichiro Yano, Kouji Nakahara, Hiroji Yamada, Shinya Kominami, Mikio Hirano:
An all DC-powered Josephson logic circuit. 1123-1132 - Kenji Sakaue, Yasuro Shobatake, Masahiko Motoyama, Yoshinari Kumaki, Satoru Takatsuka, Shigeru Tanaka, Hiroyuki Hara, Kouji Matsuda, Shuji Kitaoka, Makoto Noda, Youichiro Niitsu, Masayuki Norishima, Hiroshi Momose, Kenji Maeguchi, Manabu Ishibe, Shoichi Shimizu, Toshikazu Kodama:
A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network. 1133-1144 - Sterling R. Whitaker, Shamanna K. Manjunath, Gary K. Maki:
Sequence-invariant state machines. 1145-1151 - Shih-Lien Lu, Milos D. Ercegovac:
Evaluation of two-summand adders implemented in ECDL CMOS differential logic. 1152-1160 - Hugh McDermott:
A custom-designed receiver-stimulator chip for an advanced multiple-channel hearing prosthesis. 1161-1164 - Abdellatif Bellaouar, Mohamed I. Elmasry:
BiCMOS nonthreshold logic for high-speed low-power applications. 1165-1167 - Morteza Afghahi, Jiren Yuan:
Double-edge-triggered D-flip-flops for high-speed CMOS circuits. 1168-1170 - Peter Gillingham, Richard C. Foss, Valerie Lines, Gregg Shimokura, Tomasz Wojcicki:
High-speed, high-reliability circuit design for megabit DRAM. 1171-1175 - Rainer H. Derksen, Haruhiko Ichino:
Comments on '18-GHz 1/8 dynamic frequency divider using Si bipolar technologies (and reply). 1176
Volume 26, Number 9, September 1991
- Paul J. Song, Giovanni De Micheli:
Circuit and architecture trade-offs for high-speed multiplication. 1184-1198 - Douglas J. Fouts, Steven E. Butner:
Architecture and design of a 500-MHz gallium-arsenide processing element for a parallel supercomputer. 1199-1211 - Sy-Yen Kuo, Sheng-Chiech Liang:
Defect-tolerant hierarchical sorting networks for wafer-scale integration. 1212-1222 - Derek B. I. Feltham, Wojciech Maly:
Physically realistic fault models for analog CMOS neural networks. 1223-1229 - Kaushik Roy, Jacob A. Abraham:
The use of RTL descriptions in accurate timing verification and test generation (VLSI). 1230-1239 - Akhilesh Tyagi:
Energy consumption in multilective and boundary VLSI computations. 1240-1248 - John H. Pasternak, C. André T. Salama:
Design of submicrometer CMOS differential pass-transistor logic circuits. 1249-1258 - Kumar N. Ganapathy, Adit D. Singh, Dhiraj K. Pradhan:
Yield optimization in large RAM's with hierarchical redundancy. 1259-1264 - Srinivasa R. Vemuru, Arthur R. Thorbjornsen:
Variable-taper CMOS buffers. 1265-1269 - Jose Luis Merino Gonzalez, Fernando Ortiz Sienz, Gabriel Valencia Miranda:
Shumbler: a 155 Mb/s BiCMOS synchronous multiplexer chip for a broad-band customer premises network. 1270-1277 - Thu-ji Lin, Henry Samulei:
A 200-MHz CMOS x/sin(x) digital filter for compensating D/A converter frequency response distortion. 1278-1285 - Moon-Key Lee, Kyung-Wook Shin, Jang-Kyu Lee:
A VLSI array processor for 16-point FFT. 1286-1292 - Zhenhua Wang:
A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance. 1293-1301 - Yoshito Nejime, Masao Hotta, Seiichi Ueda:
An 8-b ADC with over-Nyquist input at 300-Ms/s conversion rate. 1302-1308 - John H. Pasternak, C. André T. Salama:
GaAs MESFET differential pass-transistor logic. 1309-1316 - Dirk Timmermann, Helmut Hahn, Bedrich J. Hosticka, G. Schmidt:
A programmable CORDIC chip for digital signal processing applications. 1317-1321 - Philip C. Munro, Fang-Qiu Ye:
Simulating the current mirror with a self-heating BJT model. 1321-1324 - Chung-Yu Wu, Kuo-Hsing Cheng:
Latched CMOS differential logic (LCDL) for complex high-speed VLSI. 1324-1328
Volume 26, Number 10, October 1991
- Masayuki Abe, Takashi Mimura:
Ultrahigh-speed HEMT LSI technology for supercomputer. 1337-1344 - Hans Ransijn, Paul O'Connor:
A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC. 1345-1353 - Randy B. Nubling, James Yu, Keh-Chung Wang, Peter M. Asbeck, Neng-Huang Sheng, Mau-Chung Frank Chang, Richard L. Pierson, Gerard J. Sullivan, Mark A. McDonald, A. J. Price, A. D. M. Chen:
High-speed 8:1 multiplexer and 1:8 demultiplexer implemented with AlGaAs/GaAs HBTs. 1354-1361 - Neng-Huang Sheng, Richard L. Pierson, Keh-Chung Wang, Randy B. Nubling, Peter M. Asbeck, Mau-Chung Frank Chang, W. L. Edwards, D. E. Philips:
A high-speed multimodulus HBT prescaler for frequency synthesizer applications. 1362-1367 - Hidetoshi Kawasaki, Masaru Wada, Yukio Hida, Chiaki Takano, Jiro Kasahara:
10 K-gate GaAs JFET sea of gates. 1367-1370 - Reza Majidi-Ahy, Clifford Nishimoto, Majid Riaziat, Mike Glenn, Scott Silverman, Shang-Lin Weng, Yi-Chin Pao, George Zdasiuk, Steve Bandy, Zoilo Tan:
100-GHz high-gain InP MMIC cascode amplifier. 1370-1378 - Mark Rodwell, Joseph F. Jensen, William E. Stanchina, R. A. Metzger, David B. Rensch, M. W. Pierce, T. V. Kargodorian, Y. K. Allen:
33-GHz monolithic cascode AlInAs/GaInAs heterojunction bipolar transistor feedback amplifier. 1378-1382 - Huy Minh Le, Yi-Chi Shih, Vincent D. Hwang, Tom Y. Chi, Karl J. Kasel, David C. Wang:
An X-band high-efficiency MMIC power amplifier with 20-dB return losses. 1383-1389 - Tzu-hung Chen, Thuy-Nhung Ton, Gee Samuel Dow, K. Nakano, L. C. T. Liu, John B. Berenz:
A Q-band monolithic balance resistive HEMT mixer using CPW/slotline balun. 1389-1394 - Fazal Ali, Allen Podell:
A wide-band GaAs monolithic spiral quadrature hybrid and its circuit applications. 1394-1398 - Shuichi Matsue, Hiroshi Makino, Minoru Noda, Hirofumi Nakano, Satoshi Takano, Kazuo Nishitani, Shimpei Kayano:
A 5-ns GaAs 16-kb SRAM. 1399-1406 - Richard D. Jolly:
A 9-ns, 1.4-gigabyte/s, 17-ported CMOS register file. 1407-1412 - Rahul Sarpeshkar, John L. Wyatt Jr., Nicky C. Lu, Porter D. Gerber:
Mismatch sensitivity of a simultaneously latched CMOS sense amplifier. 1413-1422 - Ahmed Boubekeur, Gabriele Saucier, Jacques Trilhe:
A reconfigurable wafer-scale memory. 1423-1432 - Lawrence K. Yu, David M. Lewis:
A 30-b integrated logarithmic number system processor. 1433-1440 - David H. K. Hoe, C. André T. Salama:
GaAs trickle transistor dynamic logic. 1441-1448 - John A. Fifield, Charles H. Stapper:
High-speed on-chip ECC for synergistic fault-tolerance memory chips. 1449-1452 - Morteza Afghahi:
A 512 16-b bit-serial sorter chip. 1452-1457 - Harald Parzhuber, Wolfgang Steinhagen:
An adaptive biasing one-stage CMOS operational amplifier for driving high capacitive loads. 1457-1460 - Chung-Yu Wu, Ping-Hsing Lu, Ming-Kai Tsai:
Design techniques for high-frequency CMOS switched-capacitor filters using non-op-amp-based unity-gain amplifiers. 1460-1466 - Norman Scheinberg, Ellis Chisholm:
A capacitance model for GaAs MESFETs. 1467-1470 - Muhammad Taher Abuelma'atti:
Modeling of loaded uniform RC lines for computer-aided analysis. 1470-1472
Volume 26, Number 11, November 1991
- Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano:
A 45-ns 64-Mb DRAM with a merged match-line test architecture. 1486-1492 - Masao Taguchi, Hiroyoshi Tomita, Toshiya Uchida, Yasuhiro Ohnishi, Kimiaki Sato, Taiji Ema, Masaaki Higashitani, Takashi Yabu:
A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture. 1493-1497 - Yukihito Oowaki, Kenji Tsuchida, Yohji Watanabe, Daisaburo Takashima, Masako Ohta, Hiroaki Nakano, Shigeyoshi Watanabe, Akihiro Nitayama, Fumio Horiguchi, Kazunori Ohuchi, Fujio Masuoka:
A 33-ns 64-Mb DRAM. 1498-1505 - Toshio Yamada, Yoshiro Nakata, Junko Hasegawa, Noriaki Amano, Akinori Shibayama, Masaru Sasago, Naoto Matsuo, Toshiki Yabu, Susumu Matsumoto, Shozo Okada, Michihiro Inoue:
A 64-Mb DRAM with meshed power line. 1506-1510 - Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto:
A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture. 1511-1518 - Walter H. Henkels, Duen-Shun Wen, Rick L. Mohler, Robert L. Franch, Thomas J. Bucelot, Christopher W. Long, John A. Bracchitta, W. J. Cote, Gary B. Bronner, Yuan Taur, Robert H. Dennard:
A 4-Mb low-temperature DRAM. 1519-1529 - Takayuki Kawahara, Yoshiki Kawajiri, Goro Kitsukawa, Yoshinobu Nakagome, Kazuhiko Sagara, Yoshifumi Kawamoto, Takesada Akiba, Shisei Kato, Yasushi Kawase, Kiyoo Itoh:
A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. 1530-1537 - Takeshi Nagai, Kenji Numata, Masaki Ogihara, Mitsuru Shimizu, Kimimasa Imai, Takahiko Hara, Munehiro Yoshida, Yoshikazu Saito, Yoshiaki Asao, Shizuo Sawada, Syuso Fujii:
A 17-ns 4-Mb CMOS DRAM. 1538-1543 - Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Gyoo Itoh, Kazuhiko Kajigaya, Atsushi Nozoe, Tetsuro Matsumoto:
Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test. 1544-1549 - Shigeru Kikuda, Hiroshi Miyamoto, Shigeru Mori, Mitsutaka Niiro, Michihiro Yamada:
Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond. 1550-1555 - Katsuyuki Sato, Kanehide Kenmizaki, Shoji Kubono, Toshio Mochizuki, Hidetomo Aoyagi, Michitaro Kanamitsu, Soichi Kunito, Hiroyuki Uchida, Yoshihiko Yasu, Atsushi Ogishima, Sho Sano, Hiroshi Kawamoto:
A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current. 1556-1562 - Shuji Murakami, Kore-aki Fujita, Motomu Ukita, Kazuhito Tsutsumi, Yasuo Inoue, Osamu Sakamoto, Motoi Ashida, Yasumasa Nishimura, Yoshio Kohno, Tadashi Nishimura, Kenji Anami:
A 21-mW 4-Mb CMOS SRAM for battery operation. 1563-1570 - Masahisa Suzuki, Seishi Notomi, Masaaki Ono, Naoki Kobayashi, Eizo Mitani, Kouichiro Odani, Takashi Mimura, Masayuki Abe:
A 1.2-ns HEMT 64-kb SRAM. 1571-1576 - Terry I. Chappell, Barbara A. Chappell, Stanley E. Schuster, James W. Allan, Stephen P. Klepner, Rajiv V. Joshi, Robert L. Franch:
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. 1577-1585 - Tsuguo Kobayashi, Kazutaka Nogami, Tsukasa Shirotori, Yukihiro Fujimoto, Yoshitaka Biwaki, Haruo Nohara, Makiji Kobayashi, Kiyoshi Kobayashi, Kazuhiro Sawada:
A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation. 1586-1592 - Naoto Tomita, Nobuaki Ohtsuka, Jun-ichi Miyamoto, Ken-ichi Imamiya, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Norihisa Arai, Yukio Kaneko, Eiji Sakagami, Kuniyoshi Yoshikawa, Sumio Tanaka:
A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique. 1593-1599 - Takeshi Nakayama, Shin'ichi Kobayashi, Yoshikazu Miyawaki, Yasushi Terada, Natsuo Ajika, Makoto Ohi, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara, Kimio Suzuki:
A 60-ns 16-Mb flash EEPROM with program and erase sequence controller. 1600-1605 - Rosalyn B. Ritts, Prasad A. Raje, James D. Plummer, Krishna C. Saraswat, Kit M. Cham:
Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossover below 2.5-V supply. 1606-1614 - Hiroyuki Hara, Takayasu Sakurai, Makoto Noda, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Yoshinori Watanabe:
0.5- mu m 2 M-transistor BiPNMOS channelless gate array. 1615-1620 - Seishi Notomi, Yuu Watanabe, Makoto Kosugi, Isamu Hanyu, Masahisa Suzuki, Takashi Mimura, Masayuki Abe:
A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates. 1621-1625 - Masakazu Kurisu, Masahiro Ohuchi, Akihiro Sawairi, Mitsuhiro Sugiyama, Hisashi Takemura, Tsutomu Tashiro:
A Si bipolar 21-GHz/320-mW static frequency divider. 1626-1631 - Yoshiki Yamauchi, Osaake Nakajima, Koichi Nagata, Masahiro Hirayama:
A 15-GHz monolithic two-modulus prescaler. 1632-1636 - Yutaka Arima, Koichiro Mashiko, Keisuke Okada, Tsuyoshi Yamada, Atsushi Maeda, Hiromi Notani, Harufusa Kondoh, Shinpei Kayano:
A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture. 1637-1644 - Gerard C. M. Gielis, Rudy J. van de Plassche, Johan van Valburg:
A 540-MHz 10-b polar-to-Cartesian converter. 1645-1650 - Ted E. Williams, Mark A. Horowitz:
A zero-overhead self-timed 160-ns 54-b CMOS divider. 1651-1661 - Hideo Nakamura, Terumi Sawase, Yasushi Akao, Shigeki Masumura, Makoto Hayashi, Hiroshi Ohsuga, Yuji Satoh, Tatsuya Aizawa:
An intelligent subprocessor for hardware emulation with 20-MOPS performance. 1662-1668 - Keh-Chung Wang, Peter M. Asbeck, Mau-Chung Frank Chang, Randy B. Nubling, Richard L. Pierson, Neng-Huang Sheng, Gerard J. Sullivan, Jimmy Yu, Andy Chen, Don Clement, Tom C.-T. Tsen, Haris F. Basit, Joseph D. George, Rock Young:
A 15-GHz gate array implemented with AlGaAs/GaAs heterojunction bipolar transistors. 1669-1672 - Robert G. Meyer, William D. Mack:
A DC to 1-GHz differential monolithic variable-gain amplifier. 1673-1680 - Zhong-Yuan Chang, Willy M. C. Sansen, Michel S. J. Steyaert:
Design considerations of high-dynamic-range wide-band amplifiers in BiCMOS technology. 1681-1688 - Nabil I. Khachab, Mohammed Ismail:
A nonlinear CMOS analog cell for VLSI signal and information processing. 1689-1699 - Satoru Aikawa, Yasuhisa Nakamura, Hitoshi Takanashi:
Multipurpose high-coding-gain 0.8- mu m BiCMOS VLSIs for high-speed multilevel trellis-coded modulation. 1700-1707 - Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi:
Quasi-complementary BiCMOS for sub-3-V digital circuits. 1708-1719 - Eric J. van der Zwan, Eric A. M. Klumperink, Evert Seevinck:
A CMOS OTA for HF filters with programmable transfer function. 1720-1723 - Ramesh Senthinathan, John L. Prince:
Simultaneous switching ground noise calculation for packaged CMOS devices. 1724-1728 - Niraj K. Jha, Qiao Tong:
Robustly testable static CMOS parity trees derived from binary decision diagrams. 1728-1733 - Jürgen Hauenschild, Hans-Martin Rein, William McFarland, D. Pettengill:
A silicon bipolar decision circuit operating up to 15 Gb/s. 1734-1736
Volume 26, Number 12, December 1991
- Brian P. Brandt, Bruce A. Wooley:
A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion. 1746-1756 - Ben M. J. Kup, Eke Carel Dijkmans, Peter J. A. Naus, Jack G. Sneep:
A bit-stream digital-to-analog converter with 18-b resolution. 1757-1763 - David B. Ribner, Richard D. Baertsch, Steven L. Garverick, Donald T. McGrath, Joseph E. Krisciunas, Toshiaki Fujii:
A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities. 1764-1774 - Hans J. Schouwenaars, D. Wouter J. Groeneveld, Cornelis A. A. Bastiaansen, Henk A. H. Termeer:
An oversampled multibit CMOS D/A converter for digital audio with 115-dB dynamic range. 1775-1780 - Chris Schiller, Pat Byrne:
A 4-GHz 8-b ADC system. 1781-1789 - Douglas A. Mercer:
A 12-b 750-ns subranging A/D converter with self-correcting S/H. 1790-1799 - Farhood Moraveji:
A high-speed current-multiplexed sample-and-hold amplifier with low hold step. 1800-1808 - Rinaldo Castello, Germano Nicollini, Pierluca Monguzzi:
A high-linearity 50- Omega CMOS differential driver for ISDN applications. 1809-1816 - Jeroen Fonderie, Johan H. Huijsing:
Operational amplifier with 1-V rail-to-rail multipath-driven output stage. 1817-1824 - Joseph N. Babanezhad:
A low-output-impedance fully differential op amp with large output swing and continuous-time common-mode feedback. 1825-1833 - Norman Scheinberg, Robert Bayruns, Timothy M. Laverick:
Monolithic GaAs transimpedance amplifiers for fiber-optic receivers. 1834-1839 - Hans-Martin Rein, Lothar Schmidt, Klaus Wörner, Wilhelm Pieper:
Wide-band symmetrical analog multiplier IC for coherent optical-fiber receivers operating up to 10 Gb/s. 1840-1846 - Shuichi Fujita, Yuhki Imai, Yasuro Yamane, Hiroshi Fushimi:
DC to 10-GHz mixer and amplifier GaAs IC's for coherent optical heterodyne receiver. 1847-1852 - David L. Standley:
An object position and orientation IC with embedded imager. 1853-1859 - Edward K. F. Lee, P. Glenn Gulak:
A CMOS field-programmable analog array. 1860-1867 - Toshihiro Minami, Ryota Kasai, Hironori Yamauchi, Yutaka Tashiro, Jun-ichi Takahashi, Shigeru Date:
A 300-MPOS video signal processor with a parallel architecture. 1868-1875 - Junichi Goto, Koichi Ando, Toshiaki Inoue, Masakazu Yamashina, Hachiro Yamada, Tadayoshi Enomoto:
250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI. 1876-1884 - Fuyuki Okamoto, Yasuhiko Hagihara, Chie Ohkubo, Naoki Nishi, Hachiro Yamada, Tadayoshi Enomoto:
A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI. 1885-1893 - Alice M. Chiang, Michael L. Chuang:
A CCD programmable image processor and its neural network applications. 1894-1901 - Yoshiyuki Matsunaga, Shinji Ohsawa:
A 1/3-in interline transfer CCD image sensor with a negative-feedback-type charge detector. 1902-1906 - Hajime Akimoto, Haruhisa Ando, Hideki Nakagawa, Yoshihiko Nakahara, Masayuki Hikiba, Hirofumi Ohta:
A 1/3-in 410000-pixel CCD image sensor with feedback field-plate amplifier. 1907-1914 - Takashi Miida, Yasumasa Hasegawa, Tatsuya Hagiwara, Hisashi Ohshiba:
A CCD video delay line with charge-integrating amplifier. 1915-1919 - Reneé G. Lerch, Matthias H. Lamkemeyer, Horst L. Fiedler, Werner Bradinal, Peter Becker:
A monolithic Sigma Delta A/D and D/A converter with filter for broad-band speech coding. 1920-1927 - Ken Buttle, Hiroshi Takatori, Cheng-Chung Shih, Haim Shafir:
A multirate transceiver IC for four-wire full-duplex data transmission. 1928-1935 - Kenji Ishida, Hirotsugu Wakimoto, Kunio Yoshihara, Mitsuo Konno, Shoichi Shimizu, Yoshiaki Kitaura, Kenichi Tomita, Takashi Suzuki, Naotaka Uchitomi:
A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONET STS-192 system. 1936-1943 - John F. Wilson, Richard Youell, Tony H. Richards, Gwilym Luff, Ralf Pilaski:
A single-chip VHF and UHF receiver for radio paging. 1944-1950 - Kadaba R. Lakshmikumar, David W. Green, Krishnaswamy Nagaraj, King-Hon Lau, Oscar E. Agazzi, Jeffrey R. Barner, Reza S. Shariatdoust, Gene A. Wilson, Tuan N. Le, M. R. Dwarakanath, Jacques G. Ruch, Jit Kumar, Timo Ali-Vehmas, Jouko J. Junkkari, Lauri Siren:
A baseband codec for digital cellular telephony. 1951-1958 - Henry T. Nicholas III, Henry Samueli:
A 150-MHz direct digital frequency synthesizer in 1.25- mu m CMOS with -90-dBc spurious performance. 1959-1969 - Bennett C. Wong, Henry Samueli:
A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications. 1970-1980 - C. Bernard Shung, Paul H. Siegel, Hemant K. Thapar, Razmik Karabed:
A 30-MHz trellis codec chip for partial-response channels. 1981-1987 - John M. Khoury:
Design of a 15-MHz CMOS continuous-time filter with on-chip tuning. 1988-1997 - Carlos H. Mastrangelo, Richard S. Muller:
Microfabricated thermal absolute-pressure sensor with on-chip digital front-end processor. 1998-2007 - Steven L. Garverick, Kenji Fujino, Donald T. McGrath, Richard D. Baertsch:
A programmable mixed-signal ASIC for power metering. 2008-2016 - Bernhard E. Boser, Eduard Sackinger, Jane Bromley, Yann LeCun, Lawrence D. Jackel:
An analog neural network processor with programmable topology. 2017-2025
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