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2020 – today
- 2022
[c37]Xiaoyuan Liu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro:
Partitioning Dense Graphs with Hardware Accelerators. ICCS (3) 2022: 476-483- [c36]Xiaoyuan Liu, Ilya Tyagin, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro:
Towards Practical Explainability with Cluster Descriptors. ICDM (Workshops) 2022: 1-10 - [c35]Hanjing Xu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh:
Scaling Vehicle Routing Problem Solvers with QUBO-based Specialized Hardware. SEC 2022: 381-386 - [i4]Xiaoyuan Liu, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro:
Partitioning Dense Graphs with Hardware Accelerators. CoRR abs/2202.09420 (2022) - [i3]Xiaoyuan Liu, Ilya Tyagin, Hayato Ushijima-Mwesigwa, Indradeep Ghosh, Ilya Safro:
Towards Practical Explainability with Cluster Descriptors. CoRR abs/2210.10662 (2022) - 2021
- [c34]Pouya Rezazadeh Kalehbasti
, Hayato Ushijima-Mwesigwa, Avradip Mandal, Indradeep Ghosh:
Ising-Based Louvain Method: Clustering Large Graphs with Specialized Hardware. IDA 2021: 350-361 - 2020
- [i2]Osman Asif Malik, Hayato Ushijima-Mwesigwa, Arnab Roy, Avradip Mandal, Indradeep Ghosh:
Binary Matrix Factorization on Special Purpose Hardware. CoRR abs/2010.08693 (2020) - [i1]Pouya Rezazadeh Kalehbasti, Hayato Ushijima-Mwesigwa, Avradip Mandal, Indradeep Ghosh:
Ising-Based Louvain Method: Clustering Large Graphs with Specialized Hardware. CoRR abs/2012.11391 (2020)
2010 – 2019
- 2017
- [j13]Hiroaki Yoshida, Guodong Li, Takuki Kamiya, Indradeep Ghosh, Sreeranga P. Rajan, Susumu Tokumoto, Kazuki Munakata, Tadahiro Uehara:
KLOVER: Automatic Test Generation for C and C Programs, Using Symbolic Execution. IEEE Softw. 34(5): 30-37 (2017) - 2016
- [c33]Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara:
FSX: fine-grained incremental unit test generation for C/C++ programs. ISSTA 2016: 106-117 - [c32]Hiroaki Yoshida, Susumu Tokumoto, Mukul R. Prasad, Indradeep Ghosh, Tadahiro Uehara:
FSX: a tool for fine-grained incremental unit test generation for C/C++ programs. SIGSOFT FSE 2016: 1052-1056 - 2015
- [c31]Cuong Nguyen, Hiroaki Yoshida, Mukul R. Prasad, Indradeep Ghosh, Koushik Sen:
Generating Succinct Test Cases Using Don't Care Analysis. ICST 2015: 1-10 - 2014
- [c30]Guodong Li, Esben Andreasen, Indradeep Ghosh:
SymJS: automatic symbolic testing of JavaScript web applications. SIGSOFT FSE 2014: 449-459 - 2013
- [c29]Guodong Li, Indradeep Ghosh:
PASS: String Solving with Parameterized Array and Interval Automaton. Haifa Verification Conference 2013: 15-31 - [c28]Guodong Li, Indradeep Ghosh:
Lazy Symbolic Execution through Abstraction and Sub-space Search. Haifa Verification Conference 2013: 295-310 - [c27]Indradeep Ghosh, Nastaran Shafiei, Guodong Li, Wei-Fan Chiang:
JST: an automatic test generation tool for industrial Java applications with strings. ICSE 2013: 992-1001 - 2012
- [c26]Guodong Li, Peng Li, Geoffrey Sawaya, Ganesh Gopalakrishnan, Indradeep Ghosh, Sreeranga P. Rajan:
GKLEE: concolic verification and test generation for GPUs. PPoPP 2012: 215-224 - 2011
- [c25]Guodong Li, Indradeep Ghosh, Sreeranga P. Rajan:
KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs. CAV 2011: 609-615
2000 – 2009
- 2009
- [c24]Sreeranga P. Rajan, Oksana Tkachuk, Mukul R. Prasad, Indradeep Ghosh, Nitin Goel, Tadahiro Uehara:
WEAVE: WEb Applications Validation Environment. ICSE Companion 2009: 101-111 - 2008
- [b1]Masahiro Fujita, Indradeep Ghosh, Mukul R. Prasad:
Verification Techniques for System-Level Design. The Morgan Kaufmann series in systems on silicon, Morgan Kaufmann 2008, ISBN 978-0-12-370616-4, pp. I-VIII, 1-240 - [c23]Xin Li, Daryl Shannon, Indradeep Ghosh, Mizuhito Ogawa, Sreeranga P. Rajan, Sarfraz Khurshid:
Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution. APLAS 2008: 36-52 - 2006
- [j12]Liang Zhang, Indradeep Ghosh, Michael S. Hsiao:
A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2526-2538 (2006) - [c22]Indradeep Ghosh, Mukul R. Prasad:
A Technique for Estimating the Difficulty of a Formal Verification Problem. ISQED 2006: 63-70 - 2005
- [c21]Indradeep Ghosh:
High Level Test Generation for Custom Hardware: An Industrial Perspective. Asian Test Symposium 2005: 458 - 2004
- [c20]Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita:
High Level Design Validation: Current Practices and Future Directions. VLSI Design 2004: 9-11 - 2003
- [c19]Farzan Fallah, Indradeep Ghosh, Masahiro Fujita:
Event-driven observability enhanced coverage analysis of C programs for functional validation. ASP-DAC 2003: 123-128 - [c18]Liang Zhang, Michael S. Hsiao, Indradeep Ghosh:
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. Asian Test Symposium 2003: 148-153 - [c17]Indradeep Ghosh, Srivaths Ravi:
On automatic generation of RTL validation test benches using circuit testing techniques. ACM Great Lakes Symposium on VLSI 2003: 289-294 - [c16]Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh:
Precomputation-based Guarding for Dynamic and Leakage Power Reduction. ICCD 2003: 90-97 - [c15]Liang Zhang, Indradeep Ghosh, Michael S. Hsiao:
Efficient Sequential ATPG for Functional RTL Circuits. ITC 2003: 290-298 - 2002
- [c14]Indradeep Ghosh, Krishna Sekar, Vamsi Boppana:
Design for Verification at the Register Transfer Level. ASP-DAC/VLSI Design 2002: 420-425 - 2001
- [j11]Indradeep Ghosh, Masahiro Fujita:
Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 402-415 (2001) - [j10]Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha:
Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1414-1425 (2001) - [c13]Farzan Fallah, Indradeep Ghosh:
Observability enhanced coverage analysis of C programs for functional validation. HLDVT 2001: 157-162 - 2000
- [j9]Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik:
A BIST scheme for RTL circuits based on symbolic testabilityanalysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(1): 111-128 (2000) - [j8]Indradeep Ghosh, Sujit Dey, Niraj K. Jha:
A fast and low-cost testing technique for core-based system-chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 863-877 (2000) - [c12]Indradeep Ghosh, Masahiro Fujita:
Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. DAC 2000: 43-48 - [c11]Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana:
A Technique for Identifying RTL and Gate-Level Correspondences. ICCD 2000: 591-594 - [c10]Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita:
Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design 2000: 436-441
1990 – 1999
- 1999
- [j7]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Hierarchical test generation and design for testability methods for ASPPs and ASIPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(3): 357-370 (1999) - [j6]Indradeep Ghosh, Niraj K. Jha, Sujit Dey:
A low overhead design for testability and test generation technique for core-based systems-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1661-1676 (1999) - 1998
- [j5]Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. J. Electron. Test. 13(2): 201-212 (1998) - [j4]Indradeep Ghosh, Niraj K. Jha:
High-level test synthesis: a survey. Integr. 26(1-2): 79-99 (1998) - [j3]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
A design-for-testability technique for register-transfer level circuits using control/data flow extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 706-723 (1998) - [c9]Indradeep Ghosh, Sujit Dey, Niraj K. Jha:
A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. DAC 1998: 542-547 - [c8]Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik:
A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. DAC 1998: 554-559 - [c7]Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey:
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. VLSI Design 1998: 193-198 - 1997
- [j2]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(9): 1001-1014 (1997) - [c6]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. DAC 1997: 534-539 - [c5]Indradeep Ghosh, Niraj K. Jha, Sujit Dey:
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. ITC 1997: 50-59 - [c4]Sudipta Bhawmik, Indradeep Ghosh:
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. VLSI Design 1997: 284-288 - 1996
- [c3]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
A design for testability technique for RTL circuits using control/data flow extraction. ICCAD 1996: 329-336 - 1995
- [j1]Indradeep Ghosh, Bandana Majumdar:
VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images. Int. J. Pattern Recognit. Artif. Intell. 9(2): 449-462 (1995) - [c2]Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha:
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ICCD 1995: 173-179 - 1994
- [c1]Indradeep Ghosh, Bandana Majumdar:
Design of an Application Specific VLSI Chip for Image Rotation. VLSI Design 1994: 275-278
Coauthor Index
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