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ORCIDJawahar Jain
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2010 – 2019
- 2013
[c41]Stergios Stergiou, Jawahar Jain:
Optimizing BDDs for time-series dataset manipulation. DATE 2013: 1018-1021- [c40]Shreyans Gandhi, Jawahar Jain, Maryam Shojaei Baghini, Soumyo Mukherji:
Comparing stress markers across various cohorts in a mobile setting. EMBC 2013: 7274-7277 - 2010
- [c39]Stergios Stergiou, Jawahar Jain:
Dynamically resizable binary decision diagrams. ACM Great Lakes Symposium on VLSI 2010: 185-190
2000 – 2009
- 2008
- [c38]Stergios Stergiou, Jawahar Jain:
Optimizing routing tables on systems-on-chip with Content-Addressable Memories. SoC 2008: 1-6 - 2006
- [j6]Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain:
On partitioning and symbolic model checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 780-788 (2006) - [c37]Stergios Stergiou, Jawahar Jain:
Disjunctive Transition Relation Decomposition for Efficient Reachability Analysis. HLDVT 2006: 29-36 - 2005
- [c36]Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu:
Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. Asian Test Symposium 2005: 460 - [c35]Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill:
A New Reachability Algorithm for Symmetric Multi-processor Architecture. ATVA 2005: 26-38 - [c34]Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle:
Error Detection Using BMC in a Parallel Environment. CHARME 2005: 354-358 - [c33]Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson:
Predictive Reachability Using a Sample-Based Approach. CHARME 2005: 388-392 - [c32]Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson:
Multi-threaded reachability. DAC 2005: 467-470 - [c31]Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain:
On Partitioning and Symbolic Model Checking. FM 2005: 497-511 - [c30]Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, E. Allen Emerson:
Under-approximation Heuristics for Grid-based Bounded Model Checking. PDMC@ICALP 2005: 31-46 - 2004
- [c29]Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson:
A Partitioning Methodology for BDD-Based Verification. FMCAD 2004: 399-413 - [c28]Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain:
Can SAT be used to Improve Sequential ATPG Methods? VLSI Design 2004: 585- - 2003
- [c27]Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain:
Improved Symbolic Verification Using Partitioning Techniques. CHARME 2003: 410-424 - [c26]Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain:
Solving the latch mapping problem in an industrial setting. DAC 2003: 442-447 - 2002
- [j5]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita:
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods Syst. Des. 21(1): 95-101 (2002) - [c25]Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain:
Improving Sequential ATPG Using SAT Methods. IWLS 2002: 79-84 - 2001
- [j4]Jawahar Jain, Ingo Wegener, Masahiro Fujita:
A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. IEEE Trans. Computers 50(11): 1289-1290 (2001) - [c24]Michael S. Hsiao, Jawahar Jain:
Practical use of sequential ATPG for model checking: going the extra mile does pay off. HLDVT 2001: 39-44 - 2000
- [c23]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita:
Automatic partitioning for efficient combinatorial verification. ASP-DAC 2000: 67-72 - [c22]Jawahar Jain, K. Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu:
Analysis of composition complexity and how to obtain smaller canonical graphs. DAC 2000: 681-686 - [c21]Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita:
Efficient variable ordering using aBDD based sampling. DAC 2000: 687-692 - [c20]Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita:
Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design 2000: 436-441 - [c19]Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao:
Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS 2000: 263-270
1990 – 1999
- 1999
- [j3]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
An efficient filter-based approach for combinational verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1542-1557 (1999) - [c18]Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni:
Multiple Error Diagnosis Based on Xlists. DAC 1999: 660-665 - [c17]Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
An Efficient Filter-Based Approach for Combinational Verification. DATE 1999: 132-137 - [c16]Rajeev Murgai, Jawahar Jain, Masahiro Fujita:
Efficient Scheduling Techniques for ROBDD Construction. VLSI Design 1999: 394-401 - 1998
- [c15]Jawahar Jain, William Adams, Masahiro Fujita:
Sampling schemes for computing OBDD variable orderings. ICCAD 1998: 631-638 - 1997
- [j2]Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell:
Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers 46(11): 1230-1245 (1997) - [c14]Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Reachability analysis using partitioned-ROBDDs. ICCAD 1997: 388-393 - [c13]Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
A Survey of Techniques for Formal Verification of Combinational Circuits. ICCD 1997: 445-454 - [c12]Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
Formal Verification of Combinational Circuit. VLSI Design 1997: 218-225 - 1996
- [c11]Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita:
Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434 - [c10]Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli:
Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. ICCAD 1996: 547-554 - [c9]Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell:
On More Efficient Combinational ATPG Using Functional Learning. VLSI Design 1996: 107-110 - [c8]Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253 - 1995
- [c7]Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita:
Advanced Verification Techniques Based on Learning. DAC 1995: 420-426 - [c6]Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita:
VERIFUL: VERIfication using FUnctional Learning. ED&TC 1995: 444-448 - [c5]Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross:
Efficient variable ordering and partial representation algorithm. VLSI Design 1995: 81-86 - 1994
- [c4]James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell:
Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS 1994: 266-275 - [c3]Jawahar Jain, James R. Bitner, Dinos Moundanos, Jacob A. Abraham, Donald S. Fussell:
A new scheme to compute variable orders for binary decision diagrams. Great Lakes Symposium on VLSI 1994: 105-108 - [c2]Rajarshi Mukherjee, Jawahar Jain, Dhiraj K. Pradhan:
Functional learning: a new approach to learning in digital circuits. VTS 1994: 122-127 - 1992
- [j1]Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell:
Probabilistic Verification of Boolean Functions. Formal Methods Syst. Des. 1(1): 61-115 (1992) - 1991
- [c1]Jawahar Jain, James R. Bitner, Donald S. Fussell, Jacob A. Abraham:
Probabilistic Design Verification. ICCAD 1991: 468-471
Coauthor Index
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