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ORCIDRajeev Murgai
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2010 – 2019
- 2018
[c43]Krishanu Debnath, Rajeev Murgai, Mayank Jain, Janet Olson:
SAT-based redundancy removal. DATE 2018: 315-318- 2015
- [j4]Rajeev Murgai:
Technology-Dependent Logic Optimization. Proc. IEEE 103(11): 2004-2020 (2015)
2000 – 2009
- 2009
- [j3]Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng:
Efficient Power Network Analysis Considering Multidomain Clock Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1348-1358 (2009) - 2008
- [c42]Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng:
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. DATE 2008: 537-540 - 2007
- [c41]Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng:
Fast power network analysis with multiple clock domains. ICCD 2007: 456-463 - [c40]Gustavo R. Wilke, Rajeev Murgai:
Design and Analysis of "Tree+Local Meshes" Clock Architecture. ISQED 2007: 165-170 - [c39]Vineet Wason, Rajeev Murgai, William W. Walker:
An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. VLSI Design 2007: 271-277 - 2006
- [c38]Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai:
Analyzing timing uncertainty in mesh-based clock architectures. DATE 2006: 1097-1102 - [c37]Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai:
Clock Distribution Architectures: A Comparative Study. ISQED 2006: 85-91 - [c36]Subodh M. Reddy, Rajeev Murgai:
Accurate Substrate Noise Analysis Based on Library Module Characterization. VLSI Design 2006: 355-362 - 2005
- [j2]Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury:
ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1): 56-64 (2005) - [c35]Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai:
A sliding window scheme for accurate clock mesh analysis. ICCAD 2005: 939-946 - [c34]Rajeev Murgai:
Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. VLSI Design 2005: 97-102 - 2004
- [c33]Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori:
Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. DATE 2004: 610-615 - [c32]Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury:
Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction. DATE 2004: 824-829 - [c31]Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma:
XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. ICCD 2004: 208-215 - [c30]Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury:
Macromodeling of digital libraries for substrate noise analysis. ISCAS (5) 2004: 516-519 - [c29]Rajeev Murgai:
Net Buffering in the Presence of Multiple Timing Views. VLSI Design 2004: 721-726 - 2003
- [j1]Arlindo L. Oliveira
, Rajeev Murgai:
On the problem of gate assignment under different rise and fall delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6): 807-814 (2003) - [c28]Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura:
PDL: A New Physical Synthesis Methodology. ISQED 2003: 348-354 - 2002
- [c27]Rajeev Murgai:
Net Buffering in the Presence of Multiple Timing Views. IWLS 2002: 367-372 - [c26]Supratik Chakraborty, Rajeev Murgai:
Layout-Driven Timing Optimization by Generalized De Morgan Transform. ASP-DAC/VLSI Design 2002: 647-654 - 2001
- [c25]Rajeev Murgai:
Efficient global fanout optimization algorithms. ASP-DAC 2001: 571-576 - [c24]Supratik Chakraborty, Rajeev Murgai:
Complexity Of Minimum-Delay Gate Resizing. VLSI Design 2001: 425-430 - 2000
- [c23]Rajeev Murgai:
Layout-Driven Area-Constrained Timing Optimization by Net Buffering. ICCAD 2000: 379-386 - [c22]Arlindo L. Oliveira, Rajeev Murgai:
An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. ICCAD 2000: 451-457 - [c21]Rajeev Murgai:
Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization. VLSI Design 2000: 240-
1990 – 1999
- 1999
- [c20]Rajeev Murgai, Masahiro Fujita:
On Reducing Transitions Through Data Modifications. DATE 1999: 82- - [c19]Rajeev Murgai:
Performance optimization under rise and fall parameters. ICCAD 1999: 185-190 - [c18]Rajeev Murgai:
On the global fanout optimization problem. ICCAD 1999: 511-515 - [c17]Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita:
Speeding Up Look-up-Table Driven Logic Simulation. VLSI 1999: 385-397 - [c16]Rajeev Murgai, Jawahar Jain, Masahiro Fujita:
Efficient Scheduling Techniques for ROBDD Construction. VLSI Design 1999: 394-401 - 1998
- [c15]Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira:
Using Complementation and Resequencing to Minimize Transitions. DAC 1998: 694-697 - 1997
- [c14]Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita:
Speeding up technology-independent timing optimization by network partitioning. ICCAD 1997: 83-90 - [c13]Rajeev Murgai, Masahiro Fujita:
Some Recent Advances in Software and Hardware Logic Simulation. VLSI Design 1997: 232-238 - 1995
- [c12]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Decomposition of logic functions for minimum transition activity. ED&TC 1995: 404-410 - [c11]Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose:
Logic synthesis for a single large look-up table. ICCD 1995: 415-424 - 1994
- [c10]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Optimum Functional Decomposition Using Encoding. DAC 1994: 408-414 - 1993
- [c9]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Sequential Synthesis for Table Look Up Programmable Gate Arrays. DAC 1993: 224-229 - [c8]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Cube-packing and two-level minimization. ICCAD 1993: 115-122 - [c7]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. ICCD 1993: 505-512 - 1992
- [c6]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
An Improved Synthesis Algorithm for Multiplexor-Based PGA's. DAC 1992: 380-386 - 1991
- [c5]Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
On Clustering for Minimum Delay/Area. ICCAD 1991: 6-9 - [c4]Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD 1991: 564-567 - [c3]Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD 1991: 572-575 - 1990
- [c2]Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Logic Synthesis for Programmable Gate Arrays. DAC 1990: 620-625
1980 – 1989
- 1989
- [c1]Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton:
SLIP: a software environment for system level interactive partitioning. ICCAD 1989: 280-283
Coauthor Index
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