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ORCIDFumiyasu Hirose
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2000 – 2009
- 2006
[e1]Fumiyasu Hirose:
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006. IEEE 2006, ISBN 0-7803-9451-8 [contents]
1990 – 1999
- 1999
- [c13]Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita:
Speeding Up Look-up-Table Driven Logic Simulation. VLSI 1999: 385-397 - 1998
- [c12]Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose:
An approach to verify a large scale system-on-a-chip using symbolic model checking. ICCD 1998: 308-313 - 1997
- [c11]Masahiro Sano, Shintaro Shimogori, Fumiyasu Hirose:
Acceleration of mincut partitioning using hardware CAD accelerator TP5000. ASP-DAC 1997: 61-64 - [c10]Minoru Shoji, Fumiyasu Hirose, Shintaro Shimogori, Satoshi Kowatari, Hiroshi Nagai:
Acceleration of behavioral simulation on simulation specific machines. ED&TC 1997: 373-377 - 1996
- [c9]Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose:
CTL model checking based on forward state traversal. ICCAD 1996: 82-87 - 1995
- [c8]Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri:
Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995: 189-190 - [c7]Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose:
Logic synthesis for a single large look-up table. ICCD 1995: 415-424 - 1994
- [c6]Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose:
Automatic test program generation for pipelined processors. ICCAD 1994: 580-583 - 1992
- [c5]Fumiyasu Hirose:
Performance Evaluation of an Event-Driven Logic Simulation Machine. DAC 1992: 428-431 - [c4]Yukiko Izuta, Fumiyasu Hirose:
Test pattern generation system for delay faults using a high speed simulation processor 'SP'. VTS 1992: 13-18 - 1990
- [j3]Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato:
A high-speed test-generation method using a test generation circuit. Syst. Comput. Jpn. 21(11): 12-20 (1990)
1980 – 1989
- 1989
- [j2]Shigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada:
Logic simulation engines in Japan. IEEE Des. Test 6(5): 40-49 (1989) - [j1]Hiroshi Yamada, Fumiyasu Hirose, Junichi Niitsuma, Tatsuya Shindo:
Simulation processor "SP". Syst. Comput. Jpn. 20(4): 71-79 (1989) - 1988
- [c3]Minoru Saitoh, Kenji Iwata, Akiko Nokamura, Makoto Kakegawa, Junichi Masuda, Hirofumi Hamamura, Fumiyasu Hirose, Nobuaki Kawato:
Logic Simulation System Using Simulation Processor (SP). DAC 1988: 225-230 - [c2]Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato:
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. ITC 1988: 102-107 - 1980
- [c1]Hiroshi Shiraishi, Fumiyasu Hirose:
Efficient placement and routing techniques for master slice LSI. DAC 1980: 458-464
Coauthor Index
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