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2020 – today
- 2022
[c8]Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang:
A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC. ISSCC 2022: 50-52
2000 – 2009
- 2007
- [j2]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Timing-Aware Power-Noise Reduction in Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 527-541 (2007) - 2006
- [c7]Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai:
Clock Distribution Architectures: A Comparative Study. ISQED 2006: 85-91 - 2005
- [c6]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Skew-programmable clock design for FPGA and skew-aware placement. FPGA 2005: 33-40 - [c5]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Timing-aware power noise reduction in layout. ICCAD 2005: 627-634 - [c4]Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai:
A sliding window scheme for accurate clock mesh analysis. ICCAD 2005: 939-946 - 2004
- [j1]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction. IEEE Trans. Very Large Scale Integr. Syst. 12(10): 1028-1037 (2004) - 2003
- [c3]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Delay budgeting in sequential circuit with application on FPGA placement. DAC 2003: 202-207 - [c2]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Minimum-Area Sequential Budgeting for FPGA. ICCAD 2003: 813-817 - [c1]Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Sequential delay budgeting with interconnect prediction. SLIP 2003: 23-30
Coauthor Index
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