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ORCIDDhiraj K. Pradhan
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- affiliation: University of Bristol, UK
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2020 – today
- 2021
[j114]Hari Mohan Gaur
, Ashutosh Kumar Singh, Anand Mohan, Masahiro Fujita, Dhiraj K. Pradhan:
Design of Single-Bit Fault-Tolerant Reversible Circuits. IEEE Des. Test 38(2): 89-96 (2021)
2010 – 2019
- 2017
- [j113]Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan:
Selected Articles from the IEEE ISED 2016 Conference. J. Low Power Electron. 13(4): 605-606 (2017) - [j112]Jimson Mathew, Rajat Subhra Chakraborty, Dhiraj K. Pradhan:
Guest Editorial: Special Issue on "Secure and Fault-Tolerant Embedded Computing". ACM Trans. Embed. Comput. Syst. 16(4): 92:1-92:2 (2017) - [j111]Mohamad Imran Bin Bandan, Samuel Nascimento Pagliarini, Jimson Mathew, Dhiraj K. Pradhan:
Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits. IEEE Trans. Reliab. 66(1): 233-244 (2017) - 2016
- [c158]Urbi Chatterjee, Rajat Subhra Chakraborty, Jimson Mathew, Dhiraj K. Pradhan:
Memristor Based Arbiter PUF: Cryptanalysis Threat and Its Mitigation. VLSID 2016: 535-540 - 2015
- [j110]Jimson Mathew, Rajat Subhra Chakraborty, Durga Prasad Sahoo, Yuanfan Yang, Dhiraj K. Pradhan:
A novel memristor based physically unclonable function. Integr. 51: 37-45 (2015) - [j109]Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan:
Selected Articles from the IEEE ISED 2014 Conference. J. Low Power Electron. 11(3): 373-374 (2015) - [j108]Jimson Mathew, Rajat Subhra Chakraborty, Durga Prasad Sahoo, Yuanfan Yang, Dhiraj K. Pradhan:
A Novel Memristor-Based Hardware Security Primitive. ACM Trans. Embed. Comput. Syst. 14(3): 60:1-60:20 (2015) - [j107]Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan:
A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection. IEEE Trans. Reliab. 64(4): 1243-1253 (2015) - [j106]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1448-1458 (2015) - [c157]Jimson Mathew, Yuamfam Yang, M. Ottavia, T. Browna, A. Zampettia, A. Di Carloa, A. M. Jabirb, Dhiraj K. Pradhan:
Fault detection and repair of DSC arrays through memristor sensing. DFTS 2015: 7-12 - [c156]Adedotun A. Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays. DFTS 2015: 17-20 - [c155]Yuanfan Yang, Jimson Mathew, Marco Ottavi, Salvatore Pontarelli, Dhiraj K. Pradhan:
2T2M memristor based TCAM cell for low power applications. DTIS 2015: 1-6 - 2014
- [j105]Yuanfan Yang, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan:
Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis. IEEE Embed. Syst. Lett. 6(1): 12-15 (2014) - [j104]Mohamad Imran Bin Bandan, Subhasis Bhattacharjee, Dhiraj K. Pradhan, Jimson Mathew:
Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System. J. Low Power Electron. 10(3): 401-416 (2014) - [j103]Luo Sun, Jimson Mathew, Samuel N. Pagliarini, Dhiraj K. Pradhan, Ioannis Sourdis:
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems. J. Low Power Electron. 10(3): 467-478 (2014) - [c154]Ioannis Sourdis, Christos Strydis, Antonino Armato, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Sebastián Isaza, Alirad Malek, R. Mariani, Samuel N. Pagliarini, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Robert M. Seepers, Rishad Ahmed Shafik, Georgios Smaragdos, Dimitris Theodoropoulos, Stavros Tzilis, Michalis Vavouras:
DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs. ARC 2014: 312-317 - [c153]Luo Sun, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan, Zhen Li:
A low power and robust carbon nanotube 6T SRAM design with metallic tolerance. DATE 2014: 1-4 - [c152]Yuanfan Yang, Jimson Mathew, Dhiraj K. Pradhan, Marco Ottavi, Salvatore Pontarelli:
Complementary resistive switch based stateful logic operations using material implication. DATE 2014: 1-4 - [c151]Jimson Mathew, Marco Ottavi, Yunfan Yang, Dhiraj K. Pradhan:
Using memristor state change behavior to identify faults in photovoltaic arrays. DFT 2014: 86-91 - [c150]Samuel N. Pagliarini, Dhiraj K. Pradhan:
A placement strategy for reducing the effects of multiple faults in digital circuits. IOLTS 2014: 69-74 - [c149]Samuel N. Pagliarini, Lirida A. B. Naviner, Jean-François Naviner, Dhiraj K. Pradhan:
A hybrid reliability assessment method and its support of sequential logic modelling. IOLTS 2014: 182-183 - [c148]Adedotun Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Write scheme for multiple Complementary Resistive Switch (CRS) cells. PATMOS 2014: 1-5 - 2013
- [j102]Jimson Mathew, Saraju P. Mohanty, Shibaji Banerjee, Dhiraj K. Pradhan, Abusaleh M. Jabir:
Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity. Comput. Electr. Eng. 39(4): 1077-1087 (2013) - [j101]Ioannis Sourdis, Christos Strydis, Antonino Armato, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Sebastián Isaza, Alirad Malek, R. Mariani, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Robert M. Seepers, Rishad A. Shafik, Kim Sunesen, Dimitris Theodoropoulos, Stavros Tzilis, Michalis Vavouras:
DeSyRe: On-demand system reliability. Microprocess. Microsystems 37(8-C): 981-1001 (2013) - [c147]Xiaoyu Huang, Jimson Mathew, Rishad A. Shafik, Subhasis Bhattacharjee, Dhiraj K. Pradhan:
A fast and Effective DFT for test and diagnosis of power switches in SoCs. DATE 2013: 1089-1092 - [c146]Rishad A. Shafik, Gerard K. Rauwerda, Jordy Potman, Kim Sunesen, Dhiraj K. Pradhan, Jimson Mathew, Ioannis Sourdis:
Software Modification Aided Transient Error Tolerance for Embedded Systems. DSD 2013: 219-226 - [c145]Li Gang, Jimson Mathew, Dhiraj K. Pradhan:
Multinomial Memristor Model for Simulations and Analysis. ISED 2013: 57-61 - [c144]Luo Sun, Jimson Mathew, Rishad A. Shafik, Dhiraj K. Pradhan:
Low Power and Robust Binary Tree SRAM Design for Embedded Systems. ISED 2013: 87-92 - [c143]Mohamad Imran Bin Bandan, Subhasis Bhattacharjee, Rishad A. Shafik, Dhiraj K. Pradhan, Jimson Mathew:
Lifetime Reliability-Aware Checkpointing Mechanism: Modelling and Analysis. ISED 2013: 128-132 - 2012
- [j100]Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan:
Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM. Integr. 45(1): 33-45 (2012) - [j99]Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits. J. Low Power Electron. 8(3): 270-282 (2012) - [c142]Ioannis Sourdis, Christos Strydis, Christos-Savvas Bouganis, Babak Falsafi, Georgi Nedeltchev Gaydadjiev, Alirad Malek, R. Mariani, Dionisios N. Pnevmatikatos, Dhiraj K. Pradhan, Gerard K. Rauwerda, Kim Sunesen, Stavros Tzilis:
The DeSyRe Project: On-Demand System Reliability. DSD 2012: 335-342 - [c141]Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
STEP: a unified design methodology for secure test and IP core protection. ACM Great Lakes Symposium on VLSI 2012: 333-338 - [c140]Jamil Galadanci, Rishad A. Shafik, Jimson Mathew, Amit Acharyya, Dhiraj K. Pradhan:
A Closed-Loop Control Strategy for Glucose Control in Artificial Pancreas Systems. ISED 2012: 295-299 - [c139]Rishad A. Shafik, Bashir M. Al-Hashimi, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework. ISVLSI 2012: 189-194 - [c138]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. VDAT 2012: 258-269 - 2011
- [j98]Jimson Mathew, Koushik Maharatna, Babita R. Jose, Hafizur Rahaman, Dhiraj K. Pradhan:
Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN. Circuits Syst. Signal Process. 30(4): 871-882 (2011) - [j97]Juan Antonio Maestro, Pedro Reviriego, Costas Argyrides, Dhiraj K. Pradhan:
Fault Tolerant Single Error Correction Encoders. J. Electron. Test. 27(2): 215-218 (2011) - [j96]Vishram Mishra, Jimson Mathew, Dhiraj K. Pradhan:
Fault-tolerant de-Bruijn graph based multipurpose architecture and routing protocol for wireless sensor networks. Int. J. Sens. Networks 10(3): 160-175 (2011) - [j95]Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski:
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electron. 7(4): 471-481 (2011) - [j94]Costas Argyrides, Raul Chipana, Fabian Vargas, Dhiraj K. Pradhan:
Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction. IEEE Trans. Reliab. 60(3): 528-537 (2011) - [j93]Costas Argyrides, Dhiraj K. Pradhan, Taskin Koçak:
Matrix Codes for Reliable and Cost Efficient Memory Chips. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 420-428 (2011) - [j92]Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan:
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1469-1480 (2011) - [j91]Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty:
A Routing-Aware ILS Design Technique. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2335-2338 (2011) - [c137]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields. ECCTD 2011: 600-603 - [c136]Mohammad Hosseinabady, Pejman Lotfi-Kamran, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan:
Single-Event Transient Analysis in High Speed Circuits. ISED 2011: 112-117 - [c135]Luo Sun, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
Statistical Blockade Method for Fast Robustness Estimation and Compensation of Nano-CMOS Arithmetic Circuits. ISED 2011: 194-199 - [c134]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty:
BCH code based multiple bit error correction in finite field multiplier circuits. ISQED 2011: 615-620 - [c133]Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski:
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. VLSI Design 2011: 304-309 - 2010
- [j90]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan:
Secure Testable S-box Architecture for Cryptographic Hardware Implementation. Comput. J. 53(5): 581-591 (2010) - [j89]Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan:
A Galois field-based logic synthesis with testability. IET Comput. Digit. Tech. 4(4): 263-273 (2010) - [j88]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability. IET Comput. Digit. Tech. 4(5): 428-437 (2010) - [j87]Taskin Koçak, Dhiraj K. Pradhan:
Introduction to design techniques for energy harvesting. ACM J. Emerg. Technol. Comput. Syst. 6(2): 4:1-4:2 (2010) - [j86]Saraju P. Mohanty, Dhiraj K. Pradhan:
ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management. ACM J. Emerg. Technol. Comput. Syst. 6(2): 8:1-8:26 (2010) - [j85]Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Elias Kougianos:
DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM. J. Low Power Electron. 6(3): 390-400 (2010) - [j84]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan:
Test Generation in Systolic Architecture for Multiplication Over GF(2 m). IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1366-1371 (2010) - [c132]Jawar Singh, Krishnan Ramakrishnan, Saurabh Mookerjea, Suman Datta, Narayanan Vijaykrishnan, Dhiraj K. Pradhan:
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications. ASP-DAC 2010: 181-186 - [c131]Andrew J. Ricketts, Jawar Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, Dhiraj K. Pradhan:
Investigating the impact of NBTI on different power saving cache strategies. DATE 2010: 592-597 - [c130]Nikolaos Mavrogiannakis, Costas Argyrides, Dhiraj K. Pradhan:
Improving reliability for bit parallel finite field multipliers using Decimal Hamming. EWDTS 2010: 69-72 - [c129]Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan:
A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM. ACM Great Lakes Symposium on VLSI 2010: 323-328 - [c128]Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan:
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. ISQED 2010: 131-138 - [c127]Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan:
P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP. ISQED 2010: 176-183 - [c126]Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan:
On the design of different concurrent EDC schemes for S-Box and GF(p). ISQED 2010: 211-218 - [c125]Savita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
Layout-aware Illinois Scan design for high fault coverage coverage. ISQED 2010: 683-688 - [c124]Costas Argyrides, Nikolaos Mavrogiannakis, Dhiraj K. Pradhan:
Improved Yield in Nanotechnology Circuits Using Non-square Meshes. ISVLSI 2010: 410-415 - [c123]Jimmy Tarrillo, Carlos Arthur Lang Lisbôa, Luigi Carro, Costas Argyrides, Dhiraj K. Pradhan:
Evaluation of a new low cost software level fault tolerance technique to cope with soft errors. LATW 2010: 1-3 - [c122]Anas Abu Taleb, Jimson Mathew, Dhiraj K. Pradhan:
Fault diagnosis in multi layered De Bruijn based architectures for sensor networks. PerCom Workshops 2010: 456-461 - [c121]Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir:
On the synthesis of attack tolerant cryptographic hardware. VLSI-SoC 2010: 286-291 - [c120]Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan:
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM. VLSI Design 2010: 45-50 - [c119]Anas Abu Taleb, Jimson Mathew, Dhiraj K. Pradhan:
Clustered De Bruijn Based Multi Layered Architectures for Sensor Networks. WiMo 2010: 123-136
2000 – 2009
- 2009
- [j83]Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan:
Single error correctable bit parallel multipliers over GF(2m). IET Comput. Digit. Tech. 3(3): 281-288 (2009) - [j82]Dmitri Maslov, Jimson Mathew, Donny Cheung, Dhiraj K. Pradhan:
An O(m2)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF(2m)a. Quantum Inf. Comput. 9(7&8): 610-621 (2009) - [c118]Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew:
Single ended 6T SRAM with isolated read-port for low-power embedded systems. DATE 2009: 917-922 - [c117]Costas Argyrides, Carlos Arthur Lang Lisbôa, Dhiraj K. Pradhan, Luigi Carro:
A fast error correction technique for matrix multiplication algorithms. IOLTS 2009: 133-137 - [c116]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
C-testable S-box implementation for secure advanced encryption standard. IOLTS 2009: 210-211 - [c115]Costas Argyrides, Ahmad A. Al-Yamani, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan:
Increasing memory yield in future technologies through innovative design. ISQED 2009: 622-626 - [c114]Costas Argyrides, Carlos Arthur Lang Lisbôa, Dhiraj K. Pradhan, Luigi Carro:
Single element correction in sorting algorithms with minimum delay overhead. LATW 2009: 1-6 - [c113]Costas Argyrides, Giorgos Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro:
Reliability aware yield improvement technique for nanotechnology based circuits. SBCCI 2009 - [c112]Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan:
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems. VLSI Design 2009: 307-312 - 2008
- [j81]Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty:
A single ended 6T SRAM cell design for ultra-low-voltage applications. IEICE Electron. Express 5(18): 750-755 (2008) - [j80]Hongwei Zhu, Ilie I. Luican, Florin Balasa, Dhiraj K. Pradhan:
Formal Model for the Reduction of the Dynamic Energy Consumption in Multi-Layer Memory Subsystems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3559-3567 (2008) - [j79]Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan:
Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis. IET Comput. Digit. Tech. 2(2): 118-131 (2008) - [j78]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir:
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). IEEE Trans. Computers 57(9): 1289-1294 (2008) - [j77]Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 698-711 (2008) - [j76]Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan:
Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1689-1692 (2008) - [j75]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir:
C-testable bit parallel multipliers over GF(2m). ACM Trans. Design Autom. Electr. Syst. 13(1): 5:1-5:18 (2008) - [c111]Costas Argyrides, Stephania Loizidou Himona, Dhiraj K. Pradhan:
Yield improvement and power aware low cost memory chips. WREFT@CF 2008: 353-358 - [c110]Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan:
De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. DATE 2008: 1370-1373 - [c109]Dhiraj K. Pradhan:
Application of Galois Fields to Logic Synthesis. ICIIS 2008: 1- - [c108]Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. IOLTS 2008: 16-21 - [c107]Costas Argyrides, Fabian Vargas, Marlon Moraes, Dhiraj K. Pradhan:
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. IOLTS 2008: 155-160 - [c106]Jimson Mathew, Jawar Singh, Anas Abu Taleb, Dhiraj K. Pradhan:
Fault Tolerant Reversible Finite Field Arithmetic Circuits. IOLTS 2008: 188-189 - [c105]Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan:
Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS 2008: 1684-1687 - [c104]Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan:
A nano-CMOS process variation induced read failure tolerant SRAM cell. ISCAS 2008: 3334-3337 - [c103]Costas Argyrides, Stephania Loizidou, Dhiraj K. Pradhan:
Area Reliability Trade-Off in Improved Reed Muller Coding. SAMOS 2008: 116-125 - [c102]Yi Xin Su, Jimson Mathew, Jawar Singh, Dhiraj K. Pradhan:
Pseudo parallel architecture for AES with error correction. SoCC 2008: 187-190 - [c101]Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. SoCC 2008: 243-246 - [c100]Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
Failure analysis for ultra low power nano-CMOS SRAM under process variations. SoCC 2008: 251-254 - [c99]Donny Cheung, Dmitri Maslov, Jimson Mathew, Dhiraj K. Pradhan:
On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography. TQC 2008: 96-104 - [c98]Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan:
Single Error Correcting Finite Field Multipliers Over GF(2m). VLSI Design 2008: 33-38 - [c97]Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan:
Design of Reversible Finite Field Arithmetic Circuits with Error Detection. VLSI Design 2008: 453-459 - [c96]Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan:
A Galois Field Based Logic Synthesis Approach with Testability. VLSI Design 2008: 629-634 - [c95]Carlos Arthur Lang Lisbôa, Costas Argyrides, Dhiraj K. Pradhan, Luigi Carro:
Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. VTS 2008: 363-370 - [p1]Bharat Joshi, Dhiraj K. Pradhan, Jack J. Stiffler:
Fault-Tolerant Computing. Wiley Encyclopedia of Computer Science and Engineering 2008 - [i1]Costas Argyrides, Dhiraj K. Pradhan:
Multiple Event Upsets Aware FPGAs Using Protected Schemes. Fault-Tolerant Distributed Algorithms on VLSI Chips 2008 - 2007
- [j74]Abusaleh M. Jabir, Dhiraj K. Pradhan:
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields. IEEE Trans. Computers 56(8): 1119-1132 (2007) - [j73]Abusaleh M. Jabir, Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh:
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation. IEEE Trans. Computers 56(8): 1133-1145 (2007) - [j72]Ahmad A. Al-Yamani, S. Ramsundar, Dhiraj K. Pradhan:
A Defect Tolerance Scheme for Nanotechnology Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(11): 2402-2409 (2007) - [c94]Jawar Singh, Jimson Mathew, Mohammad Hosseinabady, Dhiraj K. Pradhan:
Single Event Upset Detection and Correction. ICIT 2007: 13-18 - [c93]Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan:
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. DFT 2007: 340-348 - [c92]Mohammad Hosseinabady, Mohammad Reza Kakoee, Jimson Mathew, Dhiraj K. Pradhan:
Reliable network-on-chip based on generalized de Bruijn graph. HLDVT 2007: 3-10 - [c91]Costas Argyrides, Dhiraj K. Pradhan:
Highly Reliable Power Aware Memory Design. IOLTS 2007: 189-190 - [c90]Jimson Mathew, Hafizur Rahaman, Dhiraj K. Pradhan:
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. IOLTS 2007: 207-208 - [c89]Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan:
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. IPDPS 2007: 1-6 - [c88]Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew:
Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. ISCAS 2007: 141-144 - [c87]Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan:
Multiple Upsets Tolerance in SRAM Memory. ISCAS 2007: 365-368 - [c86]R. Stapenhurst, Koushik Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan:
On the Hardware Reduction of z-Datapath of Vectoring CORDIC. ISCAS 2007: 3002-3005 - [c85]Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew:
CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. ISCAS 2007: 3675-3678 - [c84]Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan:
CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. ISCAS 2007: 3696-3699 - [c83]Hamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew:
SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. ISQED 2007: 380-385 - [c82]S. Ramsundar, Ahmad A. Al-Yamani, Dhiraj K. Pradhan:
Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm. ISQED 2007: 807-813 - [c81]Costas Argyrides, Carlos Arthur Lang Lisbôa, Luigi Carro, Dhiraj K. Pradhan:
A soft error robust and power aware memory design. SBCCI 2007: 300-305 - [c80]Costas Argyrides, Dhiraj K. Pradhan:
Improved decoding algorithm for high reliable reed muller coding. SoCC 2007: 95-98 - [c79]Costas Argyrides, Ahmad A. Al-Yamani, Dhiraj K. Pradhan:
High defect tolerant low cost memory chips. SoCC 2007: 119-122 - [c78]Babita R. Jose, Jimson Mathew, P. Mythili, Dhiraj K. Pradhan:
A triple-mode feed-forward sigma-delta modulator design for GSM / WCDMA / WLAN applications. SoCC 2007: 309-312 - [c77]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan:
Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). VLSI Design 2007: 479-484 - [c76]Hafizur Rahaman, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan:
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). VTS 2007: 422-430 - 2006
- [c75]Chunsheng Liu, Zach Link, Dhiraj K. Pradhan:
Reuse-based test access and integrated test scheduling for network-on-chip. DATE 2006: 303-308 - [c74]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m). HLDVT 2006: 48-54 - [c73]Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
An efficient technique for synthesis and optimization of polynomials in GF(2m). ICCAD 2006: 151-157 - [c72]Chunsheng Liu, Vikram Iyengar, Dhiraj K. Pradhan:
Thermal-Aware Testing of Network-on-Chip Using Multiple-Frequency Clocking. VTS 2006: 46-51 - 2005
- [j71]Dhiraj K. Pradhan, Chunsheng Liu:
EBIST: a novel test generator with built-in fault detection capability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9): 1457-1466 (2005) - [c71]Dhiraj K. Pradhan, Ashutosh Kumar Singh, T. L. Rajaprabhu, Abusaleh M. Jabir:
GASIM: a fast Galois field based simulator for functional model. HLDVT 2005: 135-142 - [c70]Dhiraj K. Pradhan, Dimitri Kagaris, Rohit Gambhir:
A Hamming Distance Based Test Pattern Generator with Improved Fault Coverage. IOLTS 2005: 221-226 - [c69]S. Chidambaram, Dimitrios Kagaris, Dhiraj K. Pradhan:
Comparative study of CA with phase shifters and GLFSRs. ITC 2005: 10 - [c68]Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea:
Recent Advances in Verification, Equivalence Checking and SAT-Solvers. VLSI Design 2005: 14 - 2004
- [j70]Subhasis Bhattacharjee, Dhiraj K. Pradhan:
LPRAM: a novel low-power high-performance RAM design with testability and scalability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 637-651 (2004) - [c67]Subhasis Bhattacharjee, Dhiraj K. Pradhan:
LPRAM: a low power DRAM with testability. ASP-DAC 2004: 390-393 - [c66]Abusaleh M. Jabir, Dhiraj K. Pradhan:
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions. DATE 2004: 1388-1389 - [c65]T. L. Rajaprabhu, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan:
MODD for CF: a representation for fast evaluation of multiple-output functions. HLDVT 2004: 61-66 - [c64]Chunsheng Liu, Hamid Sharif, Érika F. Cota, Dhiraj K. Pradhan:
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints. ITC 2004: 1369-1378 - [c63]Sathiamoorthy Subbarayan, Dhiraj K. Pradhan:
NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances. SAT 2004 - [c62]Sathiamoorthy Subbarayan, Dhiraj K. Pradhan:
NiVER: Non-increasing Variable Elimination Resolution for Preprocessing SAT Instances. SAT (Selected Papers 2004: 276-291 - 2003
- [j69]Mitrajit Chatterjee, Dhiraj K. Pradhan:
A BIST Pattern Generator Design for Near-Perfect Fault Coverage. IEEE Trans. Computers 52(12): 1543-1558 (2003) - [c61]Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty:
EBIST: A Novel Test Generator with Built-In Fault Detection Capability. DATE 2003: 10224-10229 - [c60]Dhiraj K. Pradhan:
Logic transformation and coding theory-based frameworks for Boolean satisfiability. HLDVT 2003: 57-62 - [c59]Dhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski:
Mathematical framework for representing discrete functions as word-level polynomials. HLDVT 2003: 135-139 - [c58]Elango Ganesan, Dhiraj K. Pradhan:
Wormhole routing in de Bruijn networks and hyper-de Bruijn networks. ISCAS (3) 2003: 870-873 - 2001
- [c57]Dhiraj K. Pradhan:
Logic Insertion to Speed-Up Logic Verification: A Recent Development. IOLTW 2001: 61-64 - [c56]Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma:
ATPG for Design Errors-Is It Possible? VTS 2001: 283-285 - 2000
- [j68]Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan:
Buffer Assignment Algorithms on Data Driven ASICs. IEEE Trans. Computers 49(1): 16-32 (2000) - [j67]Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan:
VERILAT: verification using logic augmentation and transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1041-1051 (2000)
1990 – 1999
- 1999
- [j66]Dhiraj K. Pradhan, Mitrajit Chatterjee:
GLFSR-a new test pattern generator for built-in-self-test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 238-247 (1999) - 1998
- [j65]Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz:
LOT: Logic Optimization with Testability. New transformations for logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5): 386-399 (1998) - [j64]Debendra Das Sharma, Dhiraj K. Pradhan:
Job Scheduling in Mesh Multicomputers. IEEE Trans. Parallel Distributed Syst. 9(1): 57-70 (1998) - 1997
- [j63]P. Krishna, Nitin H. Vaidya, Mainak Chatterjee, Dhiraj K. Pradhan:
A cluster-based approach for routing in dynamic networks. Comput. Commun. Rev. 27(2): 49-64 (1997) - [j62]Dhiraj K. Pradhan, Nitin H. Vaidya:
Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off. IEEE Trans. Computers 46(3): 372-378 (1997) - [c55]Bikram S. Bakshi, P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan:
Improving Performance of TCP over Wireless Networks. ICDCS 1997: 365-373 - 1996
- [j61]P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan:
Static and adaptive location management in mobile wireless networks. Comput. Commun. 19(4): 321-334 (1996) - [j60]Shlomi Dolev, Dhiraj K. Pradhan, Jennifer L. Welch:
Modified tree structure for location management in mobile environments. Comput. Commun. 19(4): 335-345 (1996) - [j59]Debendra Das Sharma, Dhiraj K. Pradhan:
Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability. J. Parallel Distributed Comput. 36(2): 106-118 (1996) - [j58]Sandeep K. Gupta, Dhiraj K. Pradhan:
Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. IEEE Trans. Computers 45(1): 63-73 (1996) - [j57]Nicholas S. Bowen, Dhiraj K. Pradhan:
The Effect of Program Behavior on Fault Observability. IEEE Trans. Computers 45(8): 868-880 (1996) - [j56]Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy:
A novel framework for logic verification in a synthesis environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 20-32 (1996) - [j55]Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan:
Synthesis of initializable asynchronous circuits. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 254-263 (1996) - [c54]Barun K. Kar, Mitrajit Chatterjee, Dhiraj K. Pradhan:
BIT-based weighted mean filter. EUSIPCO 1996: 1-4 - [c53]Dhiraj K. Pradhan, P. Krishna, Nitin H. Vaidya:
Recoverable Mobile Environment: Design and Trade-Off Analysis. FTCS 1996: 16-25 - [c52]Wanlin Cao, Dhiraj K. Pradhan:
Sequential redundancy identification using recursive learning. ICCAD 1996: 56-62 - [c51]Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee:
VERILAT: verification using logic augmentation and transformations. ICCAD 1996: 88-95 - [c50]Dhiraj K. Pradhan, Mitrajit Chatterjee, Madhu V. Swarna, Wolfgang Kunz:
Gate-level synthesis for low-power using new transformations. ISLPED 1996: 297-300 - [c49]Bikram S. Bakshi, P. Krishna, Dhiraj K. Pradhan, Nitin H. Vaidya:
Providing Seamless Communication in Mobile Wireless Networks. LCN 1996: 535-543 - 1995
- [j54]Jeffrey A. Clark, Dhiraj K. Pradhan:
Fault Injection: A Method for Validating Computer-System Dependability. Computer 28(6): 47-56 (1995) - [j53]Nicholas S. Bowen, Dhiraj K. Pradhan:
A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms. IEEE Trans. Computers 44(3): 408-418 (1995) - [j52]Dhiraj K. Pradhan, Jayashree Saxena:
A novel scheme to reduce test application time in circuits with full scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1577-1586 (1995) - [j51]Debendra Das Sharma, Dhiraj K. Pradhan:
Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation. IEEE Trans. Parallel Distributed Syst. 6(10): 1108-1122 (1995) - [c48]Subodh M. Reddy, Wolfgang Kunz, Dhiraj K. Pradhan:
Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment. DAC 1995: 414-419 - [c47]Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz:
LOT: logic optimization with testability-new transformations using recursive learning. ICCAD 1995: 318-325 - [c46]Shlomi Dolev, Dhiraj K. Pradhan, Jennifer L. Welch:
Modified Tree Structure for Location Management in Mobile Environments. INFOCOM 1995: 530-537 - [c45]P. Krishna, Mainak Chatterjee, Nitin H. Vaidya, Dhiraj K. Pradhan:
A Cluster-based Approach for Routing in Ad-Hoc Networks. Symposium on Mobile and Location-Independent Computing 1995: 1-10 - [c44]Mitrajit Chatterjee, Dhiraj K. Pradhan:
A novel pattern generator for near-perfect fault-coverage. VTS 1995: 417-425 - 1994
- [j50]Nitin H. Vaidya, Dhiraj K. Pradhan:
Safe System Level Diagnosis. IEEE Trans. Computers 43(3): 367-370 (1994) - [j49]Dhiraj K. Pradhan, Nitin H. Vaidya:
Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture. IEEE Trans. Computers 43(10): 1163-1174 (1994) - [j48]Wolfgang Kunz, Dhiraj K. Pradhan:
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(9): 1143-1158 (1994) - [c43]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan:
Signal Transition Graph Transformations for Initializability. EDAC-ETC-EUROASIC 1994: 670 - [c42]Dhiraj K. Pradhan, Nitin H. Vaidya:
Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off. FTCS 1994: 186-195 - [c41]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan:
Initialization Isuues in the Synthesis of Asynchronous Circuits. ICCD 1994: 447-452 - [c40]Debendra Das Sharma, G. D. Holland, Dhiraj K. Pradhan:
Subcube Level Time-Sharing in Hypercube Multicomputers. ICPP (2) 1994: 134-142 - [c39]P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan:
Recovery in Multicomputers with Finite Error Detection Latency. ICPP (2) 1994: 206-210 - [c38]Debendra Das Sharma, Dhiraj K. Pradhan:
Job Scheduling in Mesh Multicomputers. ICPP (2) 1994: 251-258 - [c37]Barun K. Kar, Khadem M. Yusuf, Dhiraj K. Pradhan:
Bit-Serial Generalized Median Filters. ISCAS 1994: 85-88 - [c36]Dhiraj K. Pradhan, Mitrajit Chatterjee:
GLFSR - A New Test Pattern Generator for Built-In Self-Test. ITC 1994: 481-490 - [c35]P. Krishna, Nitin H. Vaidya, Dhiraj K. Pradhan:
Location Management in Distributed Mobile Environments. PDIS 1994: 81-88 - [c34]Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan:
Synthesis of Initializable Asynchronous Circuits. VLSI Design 1994: 383-388 - [c33]Rajarshi Mukherjee, Jawahar Jain, Dhiraj K. Pradhan:
Functional learning: a new approach to learning in digital circuits. VTS 1994: 122-127 - 1993
- [j47]Nicholas S. Bowen, Dhiraj K. Pradhan:
Processor- and Memory-Based Checkpoint and Rollback Recovery. Computer 26(2): 22-31 (1993) - [j46]Dhiraj K. Pradhan, Fred J. Meyer:
Communication structures in fault-tolerant distributed systems. Networks 23(4): 379-389 (1993) - [j45]Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan:
Modeling Live and Dead Lines in Cache Memory Systems. IEEE Trans. Computers 42(1): 1-14 (1993) - [j44]Nitin H. Vaidya, Dhiraj K. Pradhan:
Fault-Tolerant Design Strategies for High Reliability and Safety. IEEE Trans. Computers 42(10): 1195-1206 (1993) - [j43]Wolfgang Kunz, Dhiraj K. Pradhan:
Accelerated dynamic learning for test pattern generation in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 684-694 (1993) - [j42]Elango Ganesan, Dhiraj K. Pradhan:
The Hyper-deBruijn Networks: Scalable Versatile Architecture. IEEE Trans. Parallel Distributed Syst. 4(9): 962-978 (1993) - [j41]Barun K. Kar, Dhiraj K. Pradhan:
A new algorithm for order statistic and sorting. IEEE Trans. Signal Process. 41(8): 2688-2694 (1993) - [j40]D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan:
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 546-558 (1993) - [c32]Barun K. Kar, R. C. K. Kumar, Dhiraj K. Pradhan:
An application specific processor for implementing stack filters. ASAP 1993: 196-199 - [c31]Dhiraj K. Pradhan, Debendra Das Sharma, Nitin H. Vaidya:
Roll-Forward Checkpointing Schemes. Hardware and Software Architectures for Fault Tolerance 1993: 95-116 - [c30]Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee:
Buffer assignment for data driven architectures. ICCAD 1993: 665-668 - [c29]Jayashree Saxena, Dhiraj K. Pradhan:
Desgin for Testability of Asynchronous Sequential Circuits. ICCD 1993: 518-522 - [c28]Nitin H. Vaidya, Dhiraj K. Pradhan:
Degradable Agreement in the Presence of Byzantine Faults. ICDCS 1993: 237-244 - [c27]Debendra Das Sharma, Dhiraj K. Pradhan:
Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors. ICPP (1) 1993: 118-127 - [c26]Elango Ganesan, Dhiraj K. Pradhan:
Optimal Broadcasting in Binary de Bruijn Networks and Hyper-de Bruijn Networks. IPPS 1993: 655-660 - [c25]Jayashree Saxena, Dhiraj K. Pradhan:
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits. ITC 1993: 724-733 - [c24]Debendra Das Sharma, Dhiraj K. Pradhan:
A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers. SPDP 1993: 682-689 - [c23]Barun K. Kar, Dhiraj K. Pradhan:
Scalability of Binary deBruijn Networks. SPDP 1993: 796-799 - 1992
- [j39]Nicholas S. Bowen, Dhiraj K. Pradhan:
Virtual Checkpoints: Architecture and Performance. IEEE Trans. Computers 41(5): 516-525 (1992) - [j38]Nitin H. Vaidya, Dhiraj K. Pradhan:
A new class of bit- and byte-error control codes. IEEE Trans. Inf. Theory 38(5): 1617-1623 (1992) - [c22]Yeong-Chang Maa, Dhiraj K. Pradhan, Dominique Thiébaut:
A Hierarchical Directory Scheme for Large-Scale Cache-Coherent Multipmcessors. IPPS 1992: 43-46 - [c21]Sandeep K. Gupta, Dhiraj K. Pradhan:
Can Concurrent Checkers Help BIST? ITC 1992: 140-150 - [c20]Wolfgang Kunz, Dhiraj K. Pradhan:
Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits. ITC 1992: 816-825 - [c19]Debendra Das Sharma, Dhiraj K. Pradhan:
A Novel Approach for Subcube Allocation in Hypercube Multiprocessors. SPDP 1992: 336-345 - [c18]Dhiraj K. Pradhan, Jayashree Saxena:
A design for testability scheme to reduce test application time in full scan. VTS 1992: 55-60 - 1991
- [j37]Yeong-Chang Maa, Dhiraj K. Pradhan, Dominique Thiébaut:
Two economical directory schemes for large-scale cache coherent multiprocessors. SIGARCH Comput. Archit. News 19(5): 10 (1991) - [j36]Dhiraj K. Pradhan, Sandeep K. Gupta:
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. IEEE Trans. Computers 40(6): 743-763 (1991) - [j35]Fred J. Meyer, Dhiraj K. Pradhan:
Consensus With Dual Failure Modes. IEEE Trans. Parallel Distributed Syst. 2(2): 214-222 (1991) - [c17]Nicholas S. Bowen, Dhiraj K. Pradhan:
Program Fault Tolerance Based on Memory Access Behavior. FTCS 1991: 426-435 - [c16]Nitin H. Vaidya, Dhiraj K. Pradhan:
System Level Diagnosis: Combining Detection and Location. FTCS 1991: 488-495 - [c15]Elango Ganesan, Dhiraj K. Pradhan:
The hyper-deBruijn multiprocessor networks. ICDCS 1991: 492-499 - [c14]Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan:
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. ITC 1991: 828-839 - [c13]Nicholas S. Bowen, Dhiraj K. Pradhan:
A virtual memory translation mechanism to support checkpoint and rollback recovery. SC 1991: 890-899 - [c12]Neeraj Suri, Avi Mendelson, Dhiraj K. Pradhan:
BDG-torus union graph-an efficient algorithmically specializedparallel interconnect. SPDP 1991: 407-414 - 1990
- [j34]Eiji Fujiwara, Dhiraj K. Pradhan:
Error-Control Coding in Computers. Computer 23(7): 63-72 (1990) - [j33]Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan:
Design and Analysis of a Gracefully Degrading Interleaved Memory System. IEEE Trans. Computers 39(1): 63-71 (1990) - [j32]Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky:
Aliasing Probability for Multiple Input Signature Analyzer. IEEE Trans. Computers 39(4): 586-591 (1990) - [c11]Dhiraj K. Pradhan:
Application specific VLSI architectures based on De Bruijn graphs. ASAP 1990: 628-640 - [c10]Sandeep K. Gupta, Dhiraj K. Pradhan, Sudhakar M. Reddy:
Zero aliasing compression. FTCS 1990: 254-263 - [c9]Abraham Mendelson, Dominique Thiébaut, Dhiraj K. Pradhan:
Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems. ICPP (1) 1990: 326-330
1980 – 1989
- 1989
- [j31]Abraham Mendelson, Dhiraj K. Pradhan, Adit D. Singh:
A single cached copy data coherence scheme for multiprocessor systems. SIGARCH Comput. Archit. News 17(6): 36-49 (1989) - [j30]Fred J. Meyer, Dhiraj K. Pradhan:
Dynamic Testing Strategy for Distributed Systems. IEEE Trans. Computers 38(3): 356-365 (1989) - [j29]Fred J. Meyer, Dhiraj K. Pradhan:
Modeling Defect Spatial Distribution. IEEE Trans. Computers 38(4): 538-546 (1989) - [j28]Maheswara R. Samatham, Dhiraj K. Pradhan:
The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI. IEEE Trans. Computers 38(4): 567-581 (1989) - [c8]Dhiraj K. Pradhan:
Fault-Tolerant VLSI Architectures Based on de Bruijn Graphs (Galileo in the Mid Nineties). Reliability Of Computer And Communication Networks 1989: 183-196 - 1988
- [j27]Israel Koren, Zahava Koren, Dhiraj K. Pradhan:
Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay. IEEE J. Solid State Circuits 23(3): 859-866 (1988) - [j26]Fred J. Meyer, Dhiraj K. Pradhan:
Flip-Trees: Fault-Tolerant Graphs with Wide Containers. IEEE Trans. Computers 37(4): 472-478 (1988) - [j25]Najmi T. Jarwala, Dhiraj K. Pradhan:
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's. IEEE Trans. Computers 37(10): 1235-1250 (1988) - [c7]Dhiraj K. Pradhan, Nirmala R. Kamath:
RTRAM: Reconfigurable and Testable Multi-Bit RAM Design. ITC 1988: 263-278 - [c6]Sandeep K. Gupta, Dhiraj K. Pradhan:
A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. ITC 1988: 329-342 - 1987
- [j24]Israel Koren, Dhiraj K. Pradhan:
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems. IEEE Trans. Computers 36(3): 344-355 (1987) - [c5]Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan:
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. ISCA 1987: 224-231 - 1986
- [j23]Israel Koren, Dhiraj K. Pradhan:
Yield and performance enhancement through redundancy in VLSI and WSI multiprocessor systems. Proc. IEEE 74(5): 699-711 (1986) - 1985
- [j22]Dhiraj K. Pradhan:
Fault-Tolerant Multiprocessor Link and Bus Network Architectures. IEEE Trans. Computers 34(1): 33-45 (1985) - [j21]Dhiraj K. Pradhan:
Dynamically Restructurable Fault-Tolerant Processor Network Architectures. IEEE Trans. Computers 34(5): 434-447 (1985) - [c4]Maheswara R. Samatham, Dhiraj K. Pradhan:
The de Bruijn Multiprocessor Network: A Versatile Sorting Network. ISCA 1985: 360-367 - 1984
- [c3]Maheswara R. Samatham, Dhiraj K. Pradhan:
A Multiprocessor Network Suitable for Single-Chip VLSI Implementation. ISCA 1984: 328-337 - 1983
- [j20]Dhiraj K. Pradhan:
Sequential Network Design Using Extra Inputs for Fault Detection. IEEE Trans. Computers 32(3): 319-323 (1983) - 1982
- [j19]Bella Bose, Dhiraj K. Pradhan:
Optimal Unidirectional Error Detecting/Correcting Codes. IEEE Trans. Computers 31(6): 564-568 (1982) - [j18]Dhiraj K. Pradhan, Sudhakar M. Reddy:
A Fault-Tolerant Communication Architecture for Distributed Systems. IEEE Trans. Computers 31(9): 863-870 (1982) - [c2]Dhiraj K. Pradhan:
On a Class of Fault-Tolerant Multiprocessor Network Architectures. ICDCS 1982: 302-311 - 1981
- [c1]Kyushik Son, Dhiraj K. Pradhan:
Completely Self-Checking Checkers in PLAs. ITC 1981: 231-240 - 1980
- [j17]Dhiraj K. Pradhan:
Fault-Tolerant Computing. Computer 13(3): 6-7 (1980) - [j16]Dhiraj K. Pradhan, Jack J. Stiffler:
Error-Correcting Codes and Self-Checking Circuits. Computer 13(3): 27-37 (1980) - [j15]Kolar L. Kodandapani, Dhiraj K. Pradhan:
Undetectability of Bridging Faults and Validity of Stuck-At Fault Test Sets. IEEE Trans. Computers 29(1): 55-59 (1980) - [j14]Dhiraj K. Pradhan:
A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications. IEEE Trans. Computers 29(6): 471-481 (1980) - [j13]Dhiraj K. Pradhan, Kolar L. Kodandapani:
A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines. IEEE Trans. Computers 29(9): 777-791 (1980)
1970 – 1979
- 1978
- [j12]Dhiraj K. Pradhan:
Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays. IEEE Trans. Computers 27(2): 181-187 (1978) - [j11]Dhiraj K. Pradhan:
A Theory of Galois Switching Functions. IEEE Trans. Computers 27(3): 239-248 (1978) - [j10]Dhiraj K. Pradhan:
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design. IEEE Trans. Computers 27(5): 396-404 (1978) - [j9]Dhiraj K. Pradhan:
Fault-Tolerant Asynchronous Networks Using Read-Only Memories. IEEE Trans. Computers 27(7): 674-679 (1978) - 1977
- [j8]L. C. Chang, Dhiraj K. Pradhan:
A graph-structural approach for the generalization of data management systems. Inf. Sci. 12(1): 1-18 (1977) - [j7]M. Y. Hsiao, Arvind M. Patel, Dhiraj K. Pradhan:
Store Address Generator with On-Line Fault-Detection Capability. IEEE Trans. Computers 26(11): 1144-1151 (1977) - 1976
- [j6]Dhiraj K. Pradhan, Sudhakar M. Reddy:
Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes. IEEE Trans. Computers 25(9): 945-949 (1976) - 1975
- [j5]Dhiraj K. Pradhan, Arvind M. Patel:
Reed-Muller Like Canonic Forms for Multivalued Functions. IEEE Trans. Computers 24(2): 206-210 (1975) - 1974
- [j4]Dhiraj K. Pradhan, Sudhakar M. Reddy:
Design of Two-Level Fault-Tolerant Networks. IEEE Trans. Computers 23(1): 41-48 (1974) - [j3]Dhiraj K. Pradhan:
Fault-Tolerant Carry-Save Adders. IEEE Trans. Computers 23(12): 1320-1322 (1974) - 1973
- [j2]Dhiraj K. Pradhan, Sudhakar M. Reddy:
Fault-Tolerant Asynchronous Networks. IEEE Trans. Computers 22(7): 662-669 (1973) - 1972
- [j1]Dhiraj K. Pradhan, Sudhakar M. Reddy:
Error-Control Techniques for Logic Processors. IEEE Trans. Computers 21(12): 1331-1336 (1972)
Coauthor Index
[j113] [j112] [j111] [c158] [j110] [j109] [j108] [j107] [j106] [c157] [c156] [c155] [j105] [j104] [j103] [c153] [c152] [c151] [c148] [j102] [c147] [c146] [c145] [c144] [c143] [j99] [c141] [c140] [c139] [c138] [j98] [j96] [j95] [j92] [j91] [c137] [c136] [c135] [c134] [c133] [j90] [j89] [j88] [j84] [c126] [c125] [c122] [c121] [c119] [j83] [j82] [c118] [c116] [c112] [j78] [j77] [j75] [c110] [c108] [c106] [c105] [c104] [c102] [c101] [c100] [c99] [c98] [c97] [c96] [c94] [c92] [c90] [c88] [c86] [c85] [c83] [c78] [c77] [c76] [c74] [c73]
Rishad A. Shafik
aka: Rishad Ahmed Shafik
aka: Rishad Ahmed Shafik
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