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ORCIDShibaji Banerjee
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2010 – 2019
- 2017
[j6]Shibaji Banerjee, Jimson Mathew:
An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-Optimization. J. Low Power Electron. 13(4): 642-648 (2017)- 2013
- [j5]Jimson Mathew, Saraju P. Mohanty, Shibaji Banerjee, Dhiraj K. Pradhan, Abusaleh M. Jabir:
Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity. Comput. Electr. Eng. 39(4): 1077-1087 (2013) - 2011
- [j4]Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski:
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization. J. Low Power Electron. 7(4): 471-481 (2011) - [j3]Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty:
A Routing-Aware ILS Design Technique. IEEE Trans. Very Large Scale Integr. Syst. 19(12): 2335-2338 (2011) - [c6]Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski:
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. VLSI Design 2011: 304-309
2000 – 2009
- 2007
- [j2]Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1331-1339 (2007) - 2006
- [j1]Shibaji Banerjee, Debdeep Mukhopadhyay, C. V. G. Rao, Dipanwita Roy Chowdhury:
An integrated DFT solution for mixed-signal SOCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1368-1377 (2006) - [c5]Shibaji Banerjee, Dipanwita Roy Chowdhury:
Built-In Self-Test for Flash Memory Embedded in SoC. DELTA 2006: 379-384 - [c4]Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set. VLSI Design 2006: 175-180 - 2005
- [c3]Debdeep Mukhopadhyay, Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
CryptoScan: A Secured Scan Chain Architecture. Asian Test Symposium 2005: 348-353 - [c2]Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
A programmable built-in self-test for embedded DRAMs. MTDT 2005: 58-63 - [c1]Shibaji Banerjee, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury:
Computer Aided Test (CAT) Tool for Mixed Signal SOCs. VLSI Design 2005: 787-790
Coauthor Index
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