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ORCIDAbusaleh M. Jabir
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2020 – today
- 2024
[c37]Meenakshi Devi, Saurabh Khandelwal, Marek Vidis, Tomas Plecenik, Abusaleh M. Jabir:
A Novel Digitisation Method for Pulse Switchable Memristive Chemical Sensors. DFT 2024: 1-6- [c36]Abishaan Ravikumar, Xiaohan Yang, Rajendra Prasad, RajaNataraj Sivaraj, Alexander Rast, Abusaleh M. Jabir:
An AI-Assisted Connection Weight Prediction for Regression Testing of Integrated Circuits. DFT 2024: 1-6 - 2022
- [c35]Anu Bala, Saurabh Khandelwal, Abusaleh M. Jabir, Marco Ottavi
:
Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability. IOLTS 2022: 1-5 - 2021
- [c34]Vishal Gupta, Giulio Panunzi, Saurabh Khandelwal, Eugenio Martinelli, Abusaleh M. Jabir, Marco Ottavi:
Reliability Assessment of Memristor based Gas Sensor Array. DFT 2021: 1-6 - [c33]Saurabh Khandelwal, Marco Ottavi, Eugenio Martinelli, Abusaleh M. Jabir:
A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations. IOLTS 2021: 1-4 - 2020
- [c32]Vishal Gupta, Danilo Pellegrini, Saurabh Khandelwal, Abusaleh M. Jabir, Shahar Kvatinsky, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi:
Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations. DFT 2020: 1-6 - [c31]Xiaohan Yang, Saurabh Khandelwal, Aiqi Jiang, Abusaleh M. Jabir:
A Modelling Attack Resistant Low Overhead Memristive Physical Unclonable Function. DFT 2020: 1-4 - [c30]Vishal Gupta, Saurabh Khandelwal, Giulio Panunzi, Eugenio Martinelli, Said Hamdioui, Abusaleh M. Jabir, Marco Ottavi:
Yield Estimation of a Memristive Sensor Array. IOLTS 2020: 1-2
2010 – 2019
- 2019
- [j13]Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir:
Novel techniques for memristive multifunction logic design. Integr. 65: 219-230 (2019) - [j12]Anu Bala, Xiaohan Yang, Adedotun Adeyemo, Abusaleh M. Jabir:
Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks. J. Low Power Electron. 15(2): 214-223 (2019) - [c29]Saurabh Khandelwal, Anu Bala, Vishal Gupta, Marco Ottavi, Eugenio Martinelli, Abusaleh M. Jabir:
Fault Modeling and Simulation of Memristor based Gas Sensors. IOLTS 2019: 58-59 - [c28]Marco Ottavi, Vishal Gupta, Saurabh Khandelwal, Shahar Kvatinsky, Jimson Mathew, Eugenio Martinelli, Abusaleh M. Jabir:
The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors. IOLTS 2019: 159-164 - 2018
- [c27]Anu Bala, Xiaohan Yang, Adedotun Adeyemo, Abusaleh M. Jabir:
A Memristive Activation Circuit for Deep Learning Neural Networks. ISED 2018: 1-5 - 2017
- [j11]Adedotun Adeyemo, Abusaleh M. Jabir, Jimson Mathew:
Minimising Impact of Wire Resistance in Low-Power Crossbar Array Write Scheme. J. Low Power Electron. 13(4): 649-660 (2017) - [c26]Anu Bala, Adedotun Adeyemo, Xiaohan Yang, Abusaleh M. Jabir:
Learning method for ex-situ training of memristor crossbar based multi-layer neural network. ICUMT 2017: 305-310 - [c25]Adedotun Adeyemo, Abusaleh M. Jabir, Jimson Mathew, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi:
Reliable gas sensing with memristive array. IOLTS 2017: 244-246 - [c24]Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir:
Parasitic effects on memristive logic architecture. PATMOS 2017: 1-5 - 2016
- [c23]Adedotun Adeyemo, Xiaohan Yang, Anu Bala, Jimson Mathew, Abusaleh M. Jabir:
Analytic models for crossbar read operation. IOLTS 2016: 3-4 - [c22]Adedotun Adeyemo, Xiaohan Yang, Anu Bala, Abusaleh M. Jabir:
Analytic models for crossbar write operation. ISED 2016: 313-317 - [c21]Anu Bala, Adedotun Adeyemo, Xiaohan Yang, Abusaleh M. Jabir:
High level abstraction of memristor model for neural network simulation. ISED 2016: 318-322 - [c20]Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir:
Novel memristive logic architectures. PATMOS 2016: 196-199 - 2015
- [j10]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1448-1458 (2015) - [c19]Adedotun A. Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays. DFTS 2015: 17-20 - 2014
- [c18]Adedotun Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Write scheme for multiple Complementary Resistive Switch (CRS) cells. PATMOS 2014: 1-5 - 2013
- [j9]Jimson Mathew, Saraju P. Mohanty, Shibaji Banerjee, Dhiraj K. Pradhan, Abusaleh M. Jabir:
Attack tolerant cryptographic hardware design by combining error correction and uniform switching activity. Comput. Electr. Eng. 39(4): 1077-1087 (2013) - 2012
- [c17]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty:
Low complexity cross parity codes for multiple and random bit error correction. ISQED 2012: 57-62 - [c16]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty:
An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies. ISVLSI 2012: 141-146 - [c15]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. VDAT 2012: 258-269 - 2011
- [c14]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
A dynamically error correctable bit parallel Montgomery multiplier over binary extension fields. ECCTD 2011: 600-603 - [c13]Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty:
BCH code based multiple bit error correction in finite field multiplier circuits. ISQED 2011: 615-620 - 2010
- [j8]Jimson Mathew, Abusaleh M. Jabir, Ashutosh Kumar Singh, Hafizur Rahaman, Dhiraj K. Pradhan:
A Galois field-based logic synthesis with testability. IET Comput. Digit. Tech. 4(4): 263-273 (2010) - [j7]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability. IET Comput. Digit. Tech. 4(5): 428-437 (2010) - [c12]Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan:
On the design of different concurrent EDC schemes for S-Box and GF(p). ISQED 2010: 211-218 - [c11]Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir:
On the synthesis of attack tolerant cryptographic hardware. VLSI-SoC 2010: 286-291
2000 – 2009
- 2009
- [j6]Jimson Mathew, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan:
Single error correctable bit parallel multipliers over GF(2m). IET Comput. Digit. Tech. 3(3): 281-288 (2009) - [c10]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
C-testable S-box implementation for secure advanced encryption standard. IOLTS 2009: 210-211 - 2008
- [j5]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir:
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). IEEE Trans. Computers 57(9): 1289-1294 (2008) - [j4]Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
GfXpress: A Technique for Synthesis and Optimization of GF(2m) Polynomials. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(4): 698-711 (2008) - [j3]Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir:
C-testable bit parallel multipliers over GF(2m). ACM Trans. Design Autom. Electr. Syst. 13(1): 5:1-5:18 (2008) - [c9]Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection. IOLTS 2008: 16-21 - [c8]Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan:
Fault tolerant bit parallel finite field multipliers using LDPC codes. ISCAS 2008: 1684-1687 - [c7]Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan:
Single Error Correcting Finite Field Multipliers Over GF(2m). VLSI Design 2008: 33-38 - [c6]Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan:
A Galois Field Based Logic Synthesis Approach with Testability. VLSI Design 2008: 629-634 - 2007
- [j2]Abusaleh M. Jabir, Dhiraj K. Pradhan:
A Graph-Based Unified Technique for Computing and Representing Coefficients over Finite Fields. IEEE Trans. Computers 56(8): 1119-1132 (2007) - [j1]Abusaleh M. Jabir, Dhiraj K. Pradhan, T. L. Rajaprabhu, Ashutosh Kumar Singh:
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation. IEEE Trans. Computers 56(8): 1133-1145 (2007) - 2006
- [c5]Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Easily Testable Implementation for Bit Parallel Multipliers in GF (2m). HLDVT 2006: 48-54 - [c4]Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew:
An efficient technique for synthesis and optimization of polynomials in GF(2m). ICCAD 2006: 151-157 - 2005
- [c3]Dhiraj K. Pradhan, Ashutosh Kumar Singh, T. L. Rajaprabhu, Abusaleh M. Jabir:
GASIM: a fast Galois field based simulator for functional model. HLDVT 2005: 135-142 - 2004
- [c2]Abusaleh M. Jabir, Dhiraj K. Pradhan:
MODD: A New Decision Diagram and Representation for Multiple Output Binary Functions. DATE 2004: 1388-1389 - [c1]T. L. Rajaprabhu, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan:
MODD for CF: a representation for fast evaluation of multiple-output functions. HLDVT 2004: 61-66 - 2001
- [b1]Abusaleh M. Jabir:
Logic minimization algorithms for three-level AND-OR-EXOR representations. University of Oxford, UK, 2001
Coauthor Index
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last updated on 2024-12-03 21:18 CET by the dblp team
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