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ORCIDSaurabh Khandelwal
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2020 – today
- 2024
[c12]Meenakshi Devi, Saurabh Khandelwal, Marek Vidis, Tomas Plecenik, Abusaleh M. Jabir:
A Novel Digitisation Method for Pulse Switchable Memristive Chemical Sensors. DFT 2024: 1-6- [c11]Vishal Gupta, Sribhuvaneshwari H, Tanmaya Kumar Das, Saurabh Khandelwal, Shyam Akashe:
Innovative Circuit Level Methodology for FinFET based Low-Power 6T SRAM Cell Design. VDAT 2024: 1-5 - 2022
- [c10]Anu Bala, Saurabh Khandelwal, Abusaleh M. Jabir, Marco Ottavi
:
Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability. IOLTS 2022: 1-5 - 2021
- [c9]Vishal Gupta, Giulio Panunzi, Saurabh Khandelwal, Eugenio Martinelli, Abusaleh M. Jabir, Marco Ottavi:
Reliability Assessment of Memristor based Gas Sensor Array. DFT 2021: 1-6 - [c8]Saurabh Khandelwal, Marco Ottavi, Eugenio Martinelli, Abusaleh M. Jabir:
A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations. IOLTS 2021: 1-4 - 2020
- [c7]Vishal Gupta, Danilo Pellegrini, Saurabh Khandelwal, Abusaleh M. Jabir, Shahar Kvatinsky, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi:
Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations. DFT 2020: 1-6 - [c6]Xiaohan Yang, Saurabh Khandelwal, Aiqi Jiang, Abusaleh M. Jabir:
A Modelling Attack Resistant Low Overhead Memristive Physical Unclonable Function. DFT 2020: 1-4 - [c5]Vishal Gupta, Saurabh Khandelwal, Giulio Panunzi, Eugenio Martinelli, Said Hamdioui, Abusaleh M. Jabir, Marco Ottavi:
Yield Estimation of a Memristive Sensor Array. IOLTS 2020: 1-2
2010 – 2019
- 2019
- [c4]Saurabh Khandelwal, Anu Bala, Vishal Gupta, Marco Ottavi, Eugenio Martinelli, Abusaleh M. Jabir:
Fault Modeling and Simulation of Memristor based Gas Sensors. IOLTS 2019: 58-59 - [c3]Marco Ottavi, Vishal Gupta, Saurabh Khandelwal, Shahar Kvatinsky, Jimson Mathew, Eugenio Martinelli, Abusaleh M. Jabir:
The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors. IOLTS 2019: 159-164 - 2018
- [c2]Vishal Gupta, Saurabh Khandelwal, Jimson Mathew, Marco Ottavi:
45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control. DFT 2018: 1-6 - 2016
- [j2]Pawan Sharma, Saurabh Khandelwal, Shyam Akashe:
FinFET Design Considerations Based on Schmitt Trigger with Slew Rate and Gain-Bandwidth Product Analysis. Wirel. Pers. Commun. 87(1): 83-97 (2016) - 2015
- [j1]Pooja Joshi, Saurabh Khandelwal, Shyam Akashe:
Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL. J. Low Power Electron. 11(3): 298-307 (2015) - 2012
- [c1]Sushil Bhushan, Saurabh Khandelwal, Balwinder Raj:
Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction. BIC-TA (2) 2012: 89-100
Coauthor Index
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