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ORCIDShyam Akashe
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2020 – today
- 2024
[c15]Vishal Gupta, Sribhuvaneshwari H, Tanmaya Kumar Das, Saurabh Khandelwal, Shyam Akashe:
Innovative Circuit Level Methodology for FinFET based Low-Power 6T SRAM Cell Design. VDAT 2024: 1-5
2010 – 2019
- 2018
- [j13]Peter Bukelani Musiiwa, Shyam Akashe
:
Holding State Performance Amelioration by Exploitation of NMOS Body Effect in 1T DRAM Cells. Wirel. Pers. Commun. 99(1): 47-66 (2018) - [j12]Mukesh Kumar Singh, Shyam Akashe:
Design and Enactment of Diverse Low Power Techniques Based Schmitt Trigger. Wirel. Pers. Commun. 101(4): 2105-2125 (2018) - 2017
- [j11]Shalini Singh, Shyam Akashe:
Low Power Consuming 1 KB (32 × 32) Memory Array Using Compact 7T SRAM Cell. Wirel. Pers. Commun. 96(1): 1099-1109 (2017) - 2016
- [j10]Peter Bukelani Musiiwa, Shyam Akashe:
Design of 8T Volatile and Non-Volatile RAM Cells with Improved Holding Phase Performance. J. Low Power Electron. 12(3): 194-204 (2016) - [j9]Pawan Sharma, Saurabh Khandelwal, Shyam Akashe:
FinFET Design Considerations Based on Schmitt Trigger with Slew Rate and Gain-Bandwidth Product Analysis. Wirel. Pers. Commun. 87(1): 83-97 (2016) - [j8]Prateek Jain, Shyam Akashe:
An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier. Wirel. Pers. Commun. 90(4): 1673-1693 (2016) - [c14]Peter Bukelani Musiiwa, Shyam Akashe:
Design of Low Power Memristor Non-Volatile Dram Cell with Footer Switch. ICTCS 2016: 90:1-90:6 - [c13]Akanksha Singh, Ayushi Marwah, Shyam Akashe:
Novel Gating Technique in D-Latch for Low Power Application. ICTCS 2016: 91:1-91:5 - [c12]Nilotpal Arjun, Ayushi Marwah, Shyam Akashe:
Realization of Schmitt Trigger in Low Power SRAM Cell. ICTCS 2016: 92:1-92:5 - [c11]Aditya Raj, Shyam Akashe:
Power and Area Efficient Capacitor Multiplier Technique for Multi-Fin Two Stage Opamp. ICTCS 2016: 93:1-93:5 - [c10]Prateek Tiwari, Ranjeet Singh Tomar, Shyam Akashe:
Power efficient optimal Operational Transconductance Amplifier Using Source Degeneration Technique. ICTCS 2016: 94:1-94:6 - [c9]Devansh Sinha, Shyam Akashe:
Design of low power 3-bit TIQ based ADC by using FinFET Technology. ICTCS 2016: 95:1-95:4 - [c8]Mohit Vyas, Shyam Akashe:
Performance Augmentation of 2: 1 Mux Using Transmission Gate. ICTCS 2016: 96:1-96:5 - [c7]Shubham Kumar, Prateek Jain, Shyam Akashe:
Design and Analysis of New Efficient Multifin Low Leakage Switch Mode Power Supply. ICTCS 2016: 97:1-97:5 - [c6]Jainendra Tripathi, Ranjeet Singh Tomar, Shyam Akashe:
A SDDG FinFET Based Op Amp with DSB Circuit. ICTCS 2016: 98:1-98:5 - 2015
- [j7]Raj Johri, Shyam Akashe, Sanjay Sharma:
High performance 8 bit cascaded carry look ahead adder with precise power consumption. Int. J. Commun. Syst. 28(8): 1475-1483 (2015) - [j6]Pooja Joshi, Saurabh Khandelwal, Shyam Akashe:
Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL. J. Low Power Electron. 11(3): 298-307 (2015) - [j5]Sheetal Soni, Shyam Akashe:
Enhanced Power Gating Schemes for Low Leakage Power and Low Ground Bounce Noise in Design of Ring Oscillator. Wirel. Pers. Commun. 80(4): 1517-1533 (2015) - 2014
- [j4]Prateek Jain, Shyam Akashe:
Analyzing the Impact of Bootstrapped ADC with Augmented NMOS Sleep Transistors Configuration on Performance Parameters. Circuits Syst. Signal Process. 33(7): 2009-2025 (2014) - [j3]Anshul Saxena, Akansha Shrivastava, Shyam Akashe:
Estimation of high performance in Schmitt triggers with stacking power-gating techniques in 45 nm CMOS technology. Int. J. Commun. Syst. 27(12): 4369-4383 (2014) - [j2]Raghvendra Singh, Shyam Akashe:
Modeling and Analysis of Low Power 10 T Full Adder with Reduced Ground Bounce noise. J. Circuits Syst. Comput. 23(1) (2014) - 2013
- [j1]Shyam Akashe, Sanjay Sharma:
Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology. Wirel. Pers. Commun. 71(1): 123-136 (2013) - 2012
- [c5]Meenakshi Mishra, Shyam Akashe, Shyam Babu:
Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4: 1 MUX in 45 nm Technology. BIC-TA (2) 2012: 139-150 - [c4]Khushboo Mishra, Shyam Akashe, Satish Kumar:
Analyzing and Minimization Effect of Temperature Variation of 2: 1 MUX Using FINFET. BIC-TA (2) 2012: 151-162 - [c3]Richa Saraswat, Shyam Akashe, Shyam Babu:
Analysis and Simulation of Full Adder Design Using MTCMOS Technique. BIC-TA (2) 2012: 189-198 - [c2]Raj Johri, Ravindra Singh Kushwah, Raghvendra Singh, Shyam Akashe:
Modeling and Simulation of High Speed 8T SRAM Cell. BIC-TA (2) 2012: 245-251 - [c1]Shyam Akashe, Rajeev Sharma, Nitesh Tiwari, Jayram Shrivas:
Implementation of 2: 4 DECODER for low leakage Using MTCMOS Technique in 45 Nanometre Regime. BIC-TA (2) 2012: 265-276
Coauthor Index
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