"Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4: 1 ..."

Meenakshi Mishra, Shyam Akashe, Shyam Babu (2012)

> Home

Details and statistics

DOI: 10.1007/978-81-322-1041-2_12

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/bic-ta/MishraAB12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/bic-ta/MishraAB12
Meenakshi Mishra, Shyam Akashe, Shyam Babu:
Effect of MT and VT CMOS, on Transmission Gate Logic for Low Power 4: 1 MUX in 45 nm Technology. BIC-TA (2) 2012: 139-150

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.