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ORCID33rd DFT 2018: Chicago, IL, USA
- 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018, Chicago, IL, USA, October 8-10, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-8398-9
- Puneet Ramesh Savanur, Spyros Tragoudas:
Threshold Voltage Extraction Using Static NBTI Aging. 1-6 - Yuta Yamamoto, Kazuteru Namba:
Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element. 1-6 - Abhishek Das, Nur A. Touba:
Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMs. 1-6 - Zois-Gerasimos Tasoulas
, Ryan Guss, Iraklis Anagnostopoulos:
Performance-Based and Aging-Aware Resource Allocation for Concurrent GPU Applications. 1-6 - Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Nestor E. Evmorfopoulos, George Dimitriou, Georgios I. Stamoulis:
A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology. 1-6 - Glenn H. Chapman, Rohan Thomas, Klinsmann J. Coelho Silva Meneses, Israel Koren, Zahava Koren:
Analysis of Single Event Upsets Based on Digital Cameras with Very Small Pixels. 1-6 - Ludovica Bozzoli, Luca Sterpone:
MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories. 1-6 - Naixing Wang, Irith Pomeranz, Brady Benware, M. Enamul Amyeen, Srikanth Venkataraman:
Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests. 1-6 - Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. 1-6 - Gianluca Furano, Antonis Tavoularis, Lucana Santos, Veronique Ferlet-Cavrois, Cesar Boatella, Ruben Garcia Alia, Pablo Fernández-Martínez, Maria Kastriotou, Vanessa Wyrwoll, Salvatore Danzeca, Maris Tali, Dejan Gacnik, Iztok Kramberger, Lars Juul, Konstantinos Maragos, George Lentaris:
FPGA SEE Test with Ultra-High Energy Heavy Ions. 1-4 - Pavan Kumar Javvaji, Spyros Tragoudas:
A Method to Model Statistical Path Delays for Accurate Defect Coverage. 1-6 - Irith Pomeranz:
Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set. 1-6 - Alexandre Coelho, Amir Charif, Nacer-Eddine Zergainoh, Raoul Velazco:
A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip. 1-6 - Semiu A. Olowogemo, William H. Robinson, Daniel B. Limbrick:
Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits. 1-6 - Danilo Pellegrini, Marco Ottavi, Eugenio Martinelli, Corrado Di Natale:
Complementary Resistive Switch Sensing. 1-5 - Vishal Gupta, Saurabh Khandelwal, Jimson Mathew, Marco Ottavi:
45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control. 1-6 - Andrea Floridia, Ernesto Sánchez:
Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors. 1-6 - Elisabeth Baseman, Nathan DeBardeleben, Sean Blanchard, Juston S. Moore, Olena Tkachenko, Kurt B. Ferreira, Taniya Siddiqua, Vilas Sridharan:
Physics-Informed Machine Learning for DRAM Error Modeling. 1-6 - Markus Schütz, Andreas Steininger, Florian Huemer, Jakob Lechner:
State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration. 1-6 - Pilin Junsangsri, Fabrizio Lombardi:
Multiple Fault Detection in Nano Programmable Logic Arrays. 1-6 - Lake Bu, Hai Cheng, Michel A. Kinsy:
Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems. 1-6 - Mark Wilkening, Fritz Previlon, David R. Kaeli, Sudhanva Gurumurthi, Steven Raasch, Vilas Sridharan:
Evaluating the Resilience of Parallel Applications. 1-6 - Zhen Gao, Lina Yan, Jinhua Zhu, Ruishi Han, Pedro Reviriego:
Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders. 1-6
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