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2010 – 2019
- 2019
[j3]Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir:
Novel techniques for memristive multifunction logic design. Integr. 65: 219-230 (2019)- [j2]Anu Bala, Xiaohan Yang, Adedotun Adeyemo, Abusaleh M. Jabir:
Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks. J. Low Power Electron. 15(2): 214-223 (2019) - 2018
- [c10]Anu Bala, Xiaohan Yang, Adedotun Adeyemo, Abusaleh M. Jabir:
A Memristive Activation Circuit for Deep Learning Neural Networks. ISED 2018: 1-5 - 2017
- [j1]Adedotun Adeyemo, Abusaleh M. Jabir, Jimson Mathew:
Minimising Impact of Wire Resistance in Low-Power Crossbar Array Write Scheme. J. Low Power Electron. 13(4): 649-660 (2017) - [c9]Anu Bala, Adedotun Adeyemo, Xiaohan Yang, Abusaleh M. Jabir:
Learning method for ex-situ training of memristor crossbar based multi-layer neural network. ICUMT 2017: 305-310 - [c8]Adedotun Adeyemo, Abusaleh M. Jabir, Jimson Mathew, Eugenio Martinelli, Corrado Di Natale, Marco Ottavi
:
Reliable gas sensing with memristive array. IOLTS 2017: 244-246 - [c7]Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir:
Parasitic effects on memristive logic architecture. PATMOS 2017: 1-5 - 2016
- [c6]Adedotun Adeyemo, Xiaohan Yang, Anu Bala, Jimson Mathew, Abusaleh M. Jabir:
Analytic models for crossbar read operation. IOLTS 2016: 3-4 - [c5]Adedotun Adeyemo, Xiaohan Yang, Anu Bala, Abusaleh M. Jabir:
Analytic models for crossbar write operation. ISED 2016: 313-317 - [c4]Anu Bala, Adedotun Adeyemo, Xiaohan Yang, Abusaleh M. Jabir:
High level abstraction of memristor model for neural network simulation. ISED 2016: 318-322 - [c3]Xiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir:
Novel memristive logic architectures. PATMOS 2016: 196-199 - 2015
- [c2]Adedotun A. Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays. DFTS 2015: 17-20 - 2014
- [c1]Adedotun Adeyemo, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Write scheme for multiple Complementary Resistive Switch (CRS) cells. PATMOS 2014: 1-5
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