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ORCIDEiji Fujiwara
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2010 – 2019
- 2010
[j27]Kazuyoshi Suzuki, Eiji Fujiwara:
MacWilliams Identity for M-Spotty Weight Enumerator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 526-531 (2010)
2000 – 2009
- 2009
- [j26]Haruhiko Kaneko, Eiji Fujiwara:
A Class of Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1508-1519 (2009) - [j25]Haruhiko Kaneko, Eiji Fujiwara:
M-Ary Substitution/Deletion/Insertion/Adjacent-Symbol-Transposition Error Correcting Codes for Data Entry Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(7): 1668-1676 (2009) - [j24]Haruhiko Kaneko, Eiji Fujiwara:
Joint source-cryptographic-channel coding for dependable systems. Int. J. Comput. Appl. Technol. 34(4): 249-256 (2009) - 2008
- [c24]Haruhiko Kaneko, Takuya Matsuzaka, Eiji Fujiwara:
Three-Level Error Control Coding for Dependable Solid-State Drives. PRDC 2008: 281-288 - 2007
- [j23]Kazuyoshi Suzuki, Toshihiko Kashiyama, Eiji Fujiwara:
A General Class of M-Spotty Byte Error Control Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(7): 1418-1427 (2007) - [j22]Kazuteru Namba, Eiji Fujiwara:
Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings. Syst. Comput. Jpn. 38(8): 54-60 (2007) - [c23]Haruhiko Kaneko, Eiji Fujiwara:
Joint Source-Cryptographic-Channel Coding Based on Linear Block Codes. AAECC 2007: 158-167 - [c22]Haruhiko Kaneko, Eiji Fujiwara:
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. DFT 2007: 349-358 - [c21]Kazuyoshi Suzuki, Haruhiko Kaneko, Eiji Fujiwara:
Mac Williams Identity for m-Spotty Weight Enumerator. ISIT 2007: 31-35 - 2006
- [j21]Kazuyoshi Suzuki, Toshihiko Kashiyama, Eiji Fujiwara:
Complex M-Spotty Byte Error Control Codes. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(9): 2396-2404 (2006) - [c20]Hiroyuki Ohde, Haruhiko Kaneko, Eiji Fujiwara:
Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems. DFT 2006: 175-183 - 2005
- [j20]Ganesan Umanesan, Eiji Fujiwara:
Parallel Decoding Cyclic Burst Error Correcting Codes. IEEE Trans. Computers 54(1): 87-92 (2005) - [c19]Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara:
Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. DFT 2005: 120-130 - [c18]Kazuyoshi Suzuki, Mamoru Shimizu, Toshihiko Kashiyama, Eiji Fujiwara:
A class of error control codes for M-spotty byte errors occurred in a limited number of bytes. ISIT 2005: 2109-2113 - [c17]Kazuyoshi Suzuki, Toshihiko Kashiyama, Eiji Fujiwara:
Complex M-spotty byte error control codes. ITW 2005: 211-215 - 2004
- [j19]Haruhiko Kaneko, Eiji Fujiwara:
A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices. IEEE Trans. Computers 53(2): 159-167 (2004) - [c16]Haruhiko Kaneko, Mariko Numakami, Eiji Fujiwara:
Nonsystematic M-Ary Asymmetric Error Correcting Codes Designed by Multilevel Coding Method. PRDC 2004: 219-226 - 2003
- [j18]Ganesan Umanesan, Eiji Fujiwara:
A Class of Codes for Correcting Single Spotty Byte Errors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(3): 704-714 (2003) - [j17]Ganesan Umanesan, Eiji Fujiwara:
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes. IEEE Trans. Computers 52(7): 835-847 (2003) - [c15]Haruhiko Kaneko, Eiji Fujiwara:
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols. DFT 2003: 242-249 - 2002
- [j16]Ganesan Umanesan, Eiji Fujiwara:
Random Double Bit Error Correcting-Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(1): 273-276 (2002) - [j15]Ganesan Umanesan, Eiji Fujiwara:
Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 490-496 (2002) - [j14]Ganesan Umanesan, Eiji Fujiwara:
Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 513-517 (2002) - [j13]Kazuteru Namba, Eiji Fujiwara:
Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1426-1430 (2002) - [c14]Ganesan Umanesan, Eiji Fujiwara:
A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems. PRDC 2002: 247-256 - 2001
- [j12]Kazuteru Namba, Eiji Fujiwara:
A class of systematic m-ary single-symbol error correcting codes. Syst. Comput. Jpn. 32(6): 21-28 (2001) - [c13]Kazuteru Namba, Eiji Fujiwara:
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. DFT 2001: 299-307 - [c12]Ganesan Umanesan, Eiji Fujiwara:
A class of systematic t/B-error correcting codes for semiconductor memory systems. ITW 2001: 85-86 - 2000
- [c11]Masato Kitakami, Hongyuan Chen, Eiji Fujiwara:
Evaluations of Burst Error Recovery for VF Arithmetic Coding. DFT 2000: 183-191 - [c10]Ganesan Umanesan, Eiji Fujiwara:
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems. DFT 2000: 192-200
1990 – 1999
- 1999
- [c9]Kiattichai Saowapa, Haruhiko Kaneko, Eiji Fujiwara:
Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability. DFT 1999: 284-292 - 1998
- [j11]Eiji Fujiwara, Tepparit Ritthongpitak, Masato Kitakami:
Optimal Two-Level Unequal Error Control Codes for Computer Systems. IEEE Trans. Computers 47(12): 1313-1325 (1998) - 1997
- [j10]Mitsuru Hamada, Eiji Fujiwara:
A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-. IEEE Trans. Computers 46(1): 105-109 (1997) - 1996
- [j9]Jien-Chung Lo, Eiji Fujiwara:
Probability to Achieve TSC Goal. IEEE Trans. Computers 45(4): 450-460 (1996) - [c8]Jien-Chung Lo, Masato Kitakami, Eiji Fujiwara:
Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study. DFT 1996: 286-294 - [c7]Tepparit Ritthongpitak, Masato Kitakami, Eiji Fujiwara:
Optimal Two-Level Unequal Error Control Codes for Computer Systems. FTCS 1996: 190-199 - 1995
- [j8]Eiji Fujiwara, Masaharu Tanaka:
Defect-Tolerant WSI File Memory System Using Address Permutation for Spare Allocation. IEICE Trans. Inf. Syst. 78-D(2): 130-137 (1995) - [j7]Eiji Fujiwara, Tsuyoshi Tanaka:
Fault-tolerant associate memories. Syst. Comput. Jpn. 26(7): 1-12 (1995) - [c6]Eiji Fujiwara, Masato Kitakami:
A Class of Optimal Fixed-Byte Error Protection Codes for Computer Systems. FTCS 1995: 310-319 - 1994
- [j6]Eiji Fujiwara, Masato Kitakami:
A class of error-correcting codes for byte-organized memory systems. IEEE Trans. Inf. Theory 40(6): 1857-1865 (1994) - 1993
- [c5]Eiji Fujiwara, Masaharu Tanaka:
A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. DFT 1993: 183-190 - [c4]Jien-Chung Lo, Eiji Fujiwara:
A Probabilistic Measurement for Totally Self-Checking Circuits. DFT 1993: 263-270 - [c3]Eiji Fujiwara, Masato Kitakami:
A Class of Error Locating Codes for Byte-Organized Memory Systems. FTCS 1993: 110-119 - 1992
- [c2]Eiji Fujiwara, Mitsuru Hamada:
Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems. FTCS 1992: 494-501 - 1990
- [j5]Eiji Fujiwara, Dhiraj K. Pradhan:
Error-Control Coding in Computers. Computer 23(7): 63-72 (1990)
1980 – 1989
- 1989
- [b1]Thammavarapu R. N. Rao, Eiji Fujiwara:
Error-control coding for computer systems. Prentice Hall 1989, ISBN 978-0-13-284068-2, pp. I-XVI, 1-524 - 1988
- [j4]Eiji Fujiwara, Kohji Matsuoka:
Fault - tolerant k - out - of - n logic unit networks. Syst. Comput. Jpn. 19(9): 21-31 (1988) - [c1]Kazumitsu Matsuzawa, Eiji Fujiwara:
Masking asymmetric line faults using semi-distance codes. FTCS 1988: 354-359 - 1987
- [j3]Eiji Fujiwara, Kohji Matsuoka:
A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing. IEEE Trans. Computers 36(1): 86-93 (1987) - 1984
- [j2]Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka:
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing. IEEE Trans. Computers 33(6): 578-583 (1984) - 1982
- [j1]Shigeo Kaneda, Eiji Fujiwara:
Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems. IEEE Trans. Computers 31(7): 596-602 (1982)
Coauthor Index
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