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ORCIDGanesan Umanesan
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2020 – today
- 2022
[c5]Steven Wei Der Chien, Artur Podobas, Martin Svedin, Andriy Tkachuk, Salem El Sayed, Pawel Andrzej Herman, Ganesan Umanesan, Sai Narasimhamurthy, Stefano Markidis:
NoaSci: A Numerical Object Array Library for I/O of Scientific Applications on Object Storage. PDP 2022: 172-176
2010 – 2019
- 2019
- [j7]Sai Narasimhamurthy, Nikita Danilov, Sining Wu, Ganesan Umanesan, Stefano Markidis, Sergio Rivas-Gomez, Ivy Bo Peng
, Erwin Laure, Dirk Pleiter, Shaun De Witt:
SAGE: Percipient Storage for Exascale Data Centric Computing. Parallel Comput. 83: 22-33 (2019) - 2018
- [c4]Sai Narasimhamurthy, Nikita Danilov, Sining Wu, Ganesan Umanesan, Steven Wei Der Chien, Sergio Rivas-Gomez, Ivy Bo Peng, Erwin Laure, Shaun De Witt, Dirk Pleiter, Stefano Markidis:
The SAGE project: a storage centric approach for exascale computing: invited paper. CF 2018: 287-292 - [i2]Sai Narasimhamurthy, Nikita Danilov, Sining Wu, Ganesan Umanesan, Stefano Markidis, Sergio Rivas-Gomez, Ivy Bo Peng, Erwin Laure, Dirk Pleiter, Shaun De Witt:
SAGE: Percipient Storage for Exascale Data Centric Computing. CoRR abs/1805.00556 (2018) - [i1]Sai Narasimhamurthy, Nikita Danilov, Sining Wu, Ganesan Umanesan, Steven Wei Der Chien, Sergio Rivas-Gomez, Ivy Bo Peng, Erwin Laure, Shaun De Witt, Dirk Pleiter, Stefano Markidis:
The SAGE Project: a Storage Centric Approach for Exascale Computing. CoRR abs/1807.03632 (2018)
2000 – 2009
- 2005
- [j6]Ganesan Umanesan, Eiji Fujiwara:
Parallel Decoding Cyclic Burst Error Correcting Codes. IEEE Trans. Computers 54(1): 87-92 (2005) - 2003
- [j5]Ganesan Umanesan, Eiji Fujiwara:
A Class of Codes for Correcting Single Spotty Byte Errors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(3): 704-714 (2003) - [j4]Ganesan Umanesan, Eiji Fujiwara:
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes. IEEE Trans. Computers 52(7): 835-847 (2003) - 2002
- [j3]Ganesan Umanesan, Eiji Fujiwara:
Random Double Bit Error Correcting-Single b-bit Byte Error Correcting (DEC-SbEC) Codes for Memory Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(1): 273-276 (2002) - [j2]Ganesan Umanesan, Eiji Fujiwara:
Adjacent Double Bit Error Correcting Codes with Single Byte Error Detecting Capability for Memory Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 490-496 (2002) - [j1]Ganesan Umanesan, Eiji Fujiwara:
Single Byte Error Correcting Codes with Double Bit within a Block Error Correcting Capability for Memory Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 513-517 (2002) - [c3]Ganesan Umanesan, Eiji Fujiwara:
A Class of Random Multiple Bits in a Byte Error Correcting (S t/b EC)Codes for Semiconductor Memory Systems. PRDC 2002: 247-256 - 2001
- [c2]Ganesan Umanesan, Eiji Fujiwara:
A class of systematic t/B-error correcting codes for semiconductor memory systems. ITW 2001: 85-86 - 2000
- [c1]Ganesan Umanesan, Eiji Fujiwara:
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems. DFT 2000: 192-200
Coauthor Index
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