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ORCIDDFT 1996: Boston, MA, USA
- 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 1996, Boston, MA, USA, November 6-8, 1996. IEEE Computer Society 1996, ISBN 0-8186-7545-4
Session 1: Defect Avoidance
- W. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider:
The Teramac Custom Computer: Extending the Limits with Defect Tolerance. 2-10 - Glenn H. Chapman, Benoit Dufort:
Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arrays. 11-20
Session 2: Yield Prediction
- Charles H. Ouyang, Witold A. Pleskacz, Wojciech Maly:
Extraction of critical areas for opens in large VLSI circuits. 21-29 - Dinesh D. Gaitonde, Wojciech Maly, D. M. H. Walker:
Fatal Fault Probability Prediction for Array Based Designs. 30-38 - Gerard A. Allan, Anthony J. Walton:
Yield Prediction by Sampling with the EYES Tool. 39-47 - Frederic Duvivier, Gerard A. Allan:
Application of a Survey Sampling Critical Area Computation Tool in a Manufacturing Environment. 48-52 - Dimitris Nikolos, Haridimos T. Vergos, Antonis Vazaios, Spyros Voulgaris:
Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches. 53-58
Session 3: Yield and Reliability Enhancement
- Thomas G. Waring, Gerard A. Allan, Anthony J. Walton:
Integration of DFM Techniques and Design Automation. 59-67 - Arunshankar Venkataraman, Israel Koren:
Trade-offs between yield and reliability enhancement [VLSI]. 68-76 - Zhan Chen, Israel Koren:
Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing. 77-85 - Wojciech Maly, Charles H. Ouyang, Subhendra Ghosh, Sury Maturi:
Detection of an antenna effect in VLSI designs. 86-95
Session 4: Layout-Driven Test
- Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
Integrated Approach for Circuit and Fault Extraction of VLSI Circuits. 96-104 - Tong Liu, Xiao-Tao Chen, Fabrizio Lombardi, José Salinas:
Layout-driven detection of bridge faults in interconnects. 105-113 - Peilin Song, Jien-Chung Lo:
Test Sequence Generation for Realistic Faults in CMOS ICs Based on Standard Cell Library. 114-123
Session 5: Process Data Analysis
- Pascal Bichebois:
Impact of Physical Defects on the Electrical Working of Embedded DRAM with 0.35B5m Design Rules. 124-130 - Allan Y. Wong:
A Statistical Parametric and Probe Yield Analysis Methodology. 131-139 - Thomas Gneiting, Ian P. Jalowiecki:
The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes. 140-148 - F. Joel Ferguson, Jianlin Yu:
Maximum Likelihood Estimation for Yield Analysis. 149-158
Session 6: Test And Diagnosis
- Thomas A. Ziaja, Earl E. Swartzlander Jr.:
Comprehensive Modeling of VLSI Test. 159-167 - Nohpill Park, Fabrizio Lombardi, Sungsoo Kim:
Modeling Quality Reduction of Multichip Module Systems due to Uneven Fault-Coverage and Imperfect Diagnosis. 168-176 - Xiaoling Sun, Wes Tutak:
Error Identification and Data Retrieval in Signature Analysis based Data Compaction. 177-184 - Claude Thibeault, A. Payeur:
Experimental Results from Iddf Testing. 185-194
Session 7: Self-Test and Self-Checking Designs
- Parag K. Lala, S. Yang, Fadi Busaba:
A unified approach for off-line and on-line testing of VLSI systems. 195-203 - Cecilia Metra, Michele Favalli, Bruno Riccò:
Compact and Highly Testable Error Indicator for Self-Checking Circuits. 204-212 - Cecilia Metra, Michele Favalli, Bruno Riccò:
Tree Checkers for Applications with Low Power-Delay Requirements. 213-220 - Stefano Barbagallo, Monica Lobetti Bodoni, Davide Medina, Gabriel de Blasio, M. Ferloni, Franco Fummi, Donatella Sciuto:
A Parametric Design of a Built-in Self-Test FIFO Embedded Memory. 221-230
Session 8: Fault-Tolerant Structuies
- Nobuo Tsuda:
Fault-Tolerant Shuffle-Exchange and de Bruijn Networks Capable of Quick Broadcasting. 231-239 - W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Fault tolerant Newton-Raphson dividers using time shared TMR. 240-248 - Anna Antola, Luca Breveglieri:
Balancing of Fault Tolerance in the New Version of the FERMI Channel Chip: a Functional Evaluation. 249-257 - Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli:
Fault detection and fault tolerance issues at CMOS level through AUED encoding. 258-267
Session 9: Reliable Circuit Synthesis
- Anna Antola, Vincenzo Piuri, Mariagiovanna Sami:
Optimizing High-Level Synthesis for Self-Checking Arithmetic Circuits. 268-276 - Cristiana Bolchini, Fabio Salice, Donatella Sciuto:
Redundant Faults in TSC Networks: Definition and Removal. 277-285 - Jien-Chung Lo, Masato Kitakami, Eiji Fujiwara:
Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study. 286-294 - Kyosun Kim, Ramesh Karri
, Miodrag Potkonjak:
Configurable Spare Processors: A New Approach to System Level-Fault Tolerance. 295-303 - X. Wendling, Raphaël Rochet, Régis Leveugle:
ROM-Based Synthesis of Fault-Tolerant Controllers. 304-309
Session 10: Fault-Tolerance Approaches
- Daniel Audet, N. Gagnon, Yvon Savaria:
Implementing Fault Injection and Tolerance Mechanisms in Multiprocessor Systems. 310-317 - Stephanie R. Goldberg, Shambhu J. Upadhyaya, W. Kent Fuchs:
Recovery Schemes for Mesh Arrays Utilizing Dedicated Spares. 318-326 - Giovanni A. Mojoli, Davide Salvi, M. G. Sami, Giacomo R. Sechi, Renato Stefanelli:
KITE: a behavioural approach to fault-tolerance in FPGA-based systems. 327-334 - Tadayoshi Horita, Itsuo Takanami:
Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults. 335-
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