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ORCIDNobuo Tsuda
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2000 – 2009
- 2002
[c8]Nobuo Tsuda:
Configurable PC Clusters Using a Hierarchical Complete-Connection-Based Switching Network. PRDC 2002: 153-162- 2001
- [c7]Nobuo Tsuda:
ABL-Tree: A Constant Diameter Interconnection Network for Reconfigurable Processor Arrays Capable of Distributed Communication . DFT 2001: 143-148 - 2000
- [j5]Nobuo Tsuda:
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring. IEEE Trans. Computers 49(5): 431-442 (2000) - [c6]Nobuo Tsuda:
Fault-Tolerant Ring- and Toroidal Mesh-Connected Processor Arrays Able to Enhance Emulation of Hypercubes. DFT 2000: 222-230 - [c5]Nobuo Tsuda, Tatsuyuki Shimizu:
Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct Replacement. ISPAN 2000: 24-29
1990 – 1999
- 1997
- [c4]Nobuo Tsuda:
Fault-Tolerant Hierarchical Interconnection Networks Constructed by Additional Bypass Linking with Graph-Node Coloring. DFT 1997: 227-233 - 1996
- [c3]Nobuo Tsuda:
Fault-Tolerant Shuffle-Exchange and de Bruijn Networks Capable of Quick Broadcasting. DFT 1996: 231-239 - 1995
- [j4]Mina Maruyama, Nobuo Tsuda, Kiyoshi Nakabayashi:
A Rule-Embedded Neural-Network and Its Effectiveness in Pattern Recognition with III-Posed Conditions. IEICE Trans. Inf. Syst. 78-D(2): 152-162 (1995) - [c2]Nobuo Tsuda, Tsutomu Ishikawa, Yukihiro Nakamura:
Totally defect-tolerant arrays capable of quick broadcasting. DFT 1995: 117-125 - 1993
- [j3]Nobuo Tsuda:
Defect- and fault-tolerant static ram module designs based on parity checking and automatic testing. Syst. Comput. Jpn. 24(2): 1-10 (1993) - [j2]Nobuo Tsuda:
Hierarchical redundancy for two-dimensional orthogonal arrays using defect-tolerant replacement circuits. Syst. Comput. Jpn. 24(2): 22-34 (1993) - [j1]Nobuo Tsuda:
Hierarchical redundancy for array-structure wsis. Syst. Comput. Jpn. 24(7): 13-30 (1993)
1980 – 1989
- 1989
- [c1]Tetsuji Satoh, Hideaki Takeda, Nobuo Tsuda:
A Compact Multiway Merge Sorter using Linear-Array Comparators. FODO 1989: 223-227
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