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2020 – today
- 2023
[j102]Yao-Ming Kuo
, Mark F. Flanagan, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro:
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension. IEEE Trans. Aerosp. Electron. Syst. 59(5): 5835-5846 (2023)- [j101]Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro:
RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography. IEEE Trans. Computers 72(3): 682-692 (2023) - 2022
- [j100]Yao-Ming Kuo, Francisco Garcia-Herrero, Oscar Ruano, Juan Antonio Maestro:
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors. Comput. Electr. Eng. 99: 107759 (2022) - [j99]Kyle W. Gear, Alfonso Sánchez-Macián, Juan Antonio Maestro:
An analysis of FPGA configuration memory SEU accumulation and a preventative scrubbing technique. Microprocess. Microsystems 90: 104467 (2022) - [j98]Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro:
ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1577-1581 (2022) - [j97]Alfonso Sánchez-Macián, Alonso Martín-Toledano, Jefferson Andres Bravo-Montes, Francisco Garcia-Herrero, Juan Antonio Maestro:
Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale. IEEE Trans. Emerg. Top. Comput. 10(2): 635-647 (2022) - 2021
- [j96]Luis Alberto Aranda, Oscar Ruano, Francisco Garcia-Herrero, Juan Antonio Maestro:
Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs. IEEE Access 9: 140676-140685 (2021) - [j95]Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro:
Low delay non-binary error correction codes based on Orthogonal Latin Squares. Integr. 76: 55-60 (2021) - [j94]Oscar Ruano, Francisco Garcia-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, Juan Antonio Maestro:
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial. Sensors 21(4): 1392 (2021) - [j93]Francisco Garcia-Herrero, Gary McGuire, Mark F. Flanagan, Alfonso Sánchez-Macián, Juan Antonio Maestro:
Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1438-1442 (2021) - [j92]Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro:
Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories. IEEE Trans. Emerg. Top. Comput. 9(4): 2139-2145 (2021) - 2020
- [j91]Luis Alberto Aranda, Francisco Garcia-Herrero, Luis Esteban, Alfonso Sánchez-Macián, Juan Antonio Maestro:
Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications. IEEE Access 8: 83167-83176 (2020) - [j90]Kyle W. Gear, Alfonso Sánchez-Macián, Francisco Garcia-Herrero, Juan Antonio Maestro:
Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA. Circuits Syst. Signal Process. 39(11): 5529-5542 (2020) - [j89]Luis Alberto Aranda, Pedro Reviriego, Juan Antonio Maestro:
Toward a Fault-Tolerant Star Tracker for Small Satellite Applications. IEEE Trans. Aerosp. Electron. Syst. 56(5): 3421-3431 (2020) - [j88]Francisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro:
Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase. IEEE Trans. Circuits Syst. 67-II(12): 3362-3366 (2020) - [j87]Luis Alberto Aranda, Alfonso Sánchez-Macián, Juan Antonio Maestro:
An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1336-1340 (2020) - [c17]Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro:
Reduction of Parity Overhead in a Subset of Orthogonal Latin Square Codes. DCIS 2020: 1-5 - [c16]Imran Wali, Alfonso Sánchez-Macián, Alexis Ramos, Juan Antonio Maestro:
Analyzing the impact of the Operating System on the Reliability of a RISC-V FPGA Implementation. ICECS 2020: 1-4
2010 – 2019
- 2019
- [j86]Luis Alberto Aranda, Alfonso Sánchez-Macián, Juan Antonio Maestro:
ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs. IEEE Access 7: 128153-128161 (2019) - [j85]Luis Alberto Aranda, Pedro Reviriego, Ricardo Gonzalez-Toral, Juan Antonio Maestro:
Protection Scheme for Star Tracker Images. IEEE Trans. Aerosp. Electron. Syst. 55(1): 486-492 (2019) - [j84]Alfonso Sánchez-Macián, Luis Alberto Aranda, Pedro Reviriego, Vahdaneh Kiani, Juan Antonio Maestro:
Enhancing Instruction TLB Resilience to Soft Errors. IEEE Trans. Computers 68(2): 214-224 (2019) - [j83]Alexis Ramos, Ricardo Gonzalez-Toral, Pedro Reviriego, Juan Antonio Maestro:
An ALU Protection Methodology for Soft Processors on SRAM-Based FPGAs. IEEE Trans. Computers 68(9): 1404-1410 (2019) - 2018
- [j82]Shanshan Liu, Pedro Reviriego, Juan Antonio Maestro, Liyi Xiao:
Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codes. Microelectron. Reliab. 81: 167-173 (2018) - [j81]Jesús Tabero, Alberto Regadío, César Pérez, Jesús Pazos, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro:
Modular fault tolerant processor architecture on a SoC for space. Microelectron. Reliab. 83: 84-90 (2018) - [j80]Ana Cóbreces, Alberto Regadío, Jesús Tabero, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro:
Seu and Sefi error detection and correction on a ddr3 memory system. Microelectron. Reliab. 91: 23-30 (2018) - [j79]Alexis Ramos, Anees Ullah, Pedro Reviriego, Juan Antonio Maestro:
Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs. IEEE Trans. Computers 67(2): 299-304 (2018) - [j78]Ricardo Gonzalez-Toral, Pedro Reviriego, Juan Antonio Maestro, Zhen Gao:
A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs. IEEE Trans. Computers 67(7): 1039-1045 (2018) - [j77]Zhen Gao, Ming Zhou, Pedro Reviriego, Juan Antonio Maestro:
Efficient Fault-Tolerant Design for Parallel Matched Filters. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 366-370 (2018) - [j76]Luis Alberto Aranda, Pedro Reviriego, Juan Antonio Maestro:
A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 376-380 (2018) - [j75]Ricardo Gonzalez-Toral, Shanshan Liu, Pedro Reviriego, Juan Antonio Maestro:
Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1293-1302 (2018) - [j74]Zhen Gao, Qingqing Jing, Yumeng Li, Pedro Reviriego, Juan Antonio Maestro:
An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications. IEEE Trans. Very Large Scale Integr. Syst. 26(1): 211-215 (2018) - 2017
- [j73]Jorge A. Martínez, Juan Antonio Maestro, Pedro Reviriego:
A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture. IEEE Comput. Archit. Lett. 16(2): 103-106 (2017) - [j72]Shanshan Liu, Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro, Liyi Xiao:
Comments on "Extend orthogonal Latin square codes for 32-bit data protection in memory applications" Microelectron. Reliab. 63 278-283 (2016). Microelectron. Reliab. 69: 126-129 (2017) - [j71]Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro:
A method to protect Cuckoo filters from soft errors. Microelectron. Reliab. 72: 85-89 (2017) - [j70]Shanshan Liu, Pedro Reviriego, Liyi Xiao, Juan Antonio Maestro:
A method to recover critical bits under a double error in SEC-DED protected memories. Microelectron. Reliab. 73: 92-96 (2017) - [j69]Alexis Ramos, Juan Antonio Maestro, Pedro Reviriego:
Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection. Microelectron. Reliab. 78: 205-211 (2017) - [j68]Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro:
Combined Modular Key and Data Error Protection for Content-Addressable Memories. IEEE Trans. Computers 66(6): 1085-1090 (2017) - [j67]Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro, Shanshan Liu:
Single Event Transient Tolerant Bloom Filter Implementations. IEEE Trans. Computers 66(10): 1831-1836 (2017) - [j66]Pedro Reviriego, Shanshan Liu, Alfonso Sánchez-Macián, Liyi Xiao, Juan Antonio Maestro:
A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes. IEEE Trans. Reliab. 66(2): 518-528 (2017) - 2016
- [j65]Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro:
Improving counting Bloom filter performance with fingerprints. Inf. Process. Lett. 116(4): 304-309 (2016) - [j64]Mustafa Demirci, Pedro Reviriego, Juan Antonio Maestro:
Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs. Microelectron. Reliab. 56: 221-227 (2016) - [j63]Pedro Reviriego, Mustafa Demirci, Jesús Tabero, Alberto Regadío, Juan Antonio Maestro:
DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs. Microelectron. Reliab. 63: 314-318 (2016) - [j62]Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro:
Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput. IEEE Trans. Computers 65(1): 326-331 (2016) - [j61]Mustafa Demirci, Pedro Reviriego, Juan Antonio Maestro:
Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes. IEEE Trans. Computers 65(9): 2932-2938 (2016) - [j60]Pedro Reviriego, Mustafa Demirci, Adrian Evans, Juan Antonio Maestro:
A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits. IEEE Trans. Circuits Syst. II Express Briefs 63-II(2): 171-175 (2016) - [j59]Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro:
Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(11): 1933-1943 (2016) - [j58]Pedro Reviriego, Kenneth J. Christensen, Juan Antonio Maestro:
A Comment on "Fast Bloom Filters and Their Generalization". IEEE Trans. Parallel Distributed Syst. 27(1): 303-304 (2016) - [j57]Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Ming Zhao, Jing Wang, Juan Antonio Maestro:
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 769-773 (2016) - [j56]Pedro Reviriego, Shanshan Liu, Liyi Xiao, Juan Antonio Maestro:
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1603-1606 (2016) - [j55]Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro:
Optimizing the Implementation of SEC-DAEC Codes in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3538-3542 (2016) - [c15]Zhen Gao, Pedro Reviriego, Juan Antonio Maestro:
Efficient fault tolerant parallel matrix-vector multiplications. IOLTS 2016: 25-26 - 2015
- [j54]Salvatore Pontarelli, Pedro Reviriego, Marco Ottavi, Juan Antonio Maestro:
Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes. IEEE Trans. Computers 64(5): 1497-1501 (2015) - [j53]Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Jing Wang, Juan Antonio Maestro:
Efficient Coding Schemes for Fault-Tolerant Parallel Filters. IEEE Trans. Circuits Syst. II Express Briefs 62-II(7): 666-670 (2015) - [j52]Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, Juan Antonio Maestro:
Fault Tolerant Parallel Filters Based on Error Correction Codes. IEEE Trans. Very Large Scale Integr. Syst. 23(2): 384-387 (2015) - [j51]Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi:
A Synergetic Use of Bloom Filters for Error Detection and Correction. IEEE Trans. Very Large Scale Integr. Syst. 23(3): 584-587 (2015) - [j50]Pedro Reviriego, Salvatore Pontarelli, Adrian Evans, Juan Antonio Maestro:
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes. IEEE Trans. Very Large Scale Integr. Syst. 23(5): 968-972 (2015) - [j49]Luis J. Saiz-Adalid, Pedro Reviriego, Pedro J. Gil, Salvatore Pontarelli, Juan Antonio Maestro:
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2332-2336 (2015) - [c14]Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi:
A method to protect Bloom filters from soft errors. DFTS 2015: 80-84 - 2014
- [j48]Vijay Sivaraman, Pedro Reviriego, Zhi Zhao, Alfonso Sánchez-Macián, Arun Vishwanath, Juan Antonio Maestro, Craig Russell:
An experimental power profile of Energy Efficient Ethernet switches. Comput. Commun. 50: 110-118 (2014) - [j47]Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro:
Energy Efficient Exact Matching for Flow Identification with Cuckoo Affinity Hashing. IEEE Commun. Lett. 18(5): 885-888 (2014) - [j46]Salvatore Pontarelli, Pedro Reviriego, Juan Antonio Maestro:
Efficient Flow Sampling With Back-Annotated Cuckoo Hashing. IEEE Commun. Lett. 18(10): 1695-1698 (2014) - [j45]Pedro Reviriego, Serdar Zafer Can, Çagri Eryilmaz, Juan Antonio Maestro, Oguz Ergin:
Exploiting processor features to implement error detection in reduced precision matrix multiplications. Microprocess. Microsystems 38(6): 581-584 (2014) - [j44]Zhen Gao, Pedro Reviriego, X. Li, Juan Antonio Maestro, Ming Zhao, J. Wang:
A fault tolerant implementation of the Goertzel algorithm. Microelectron. Reliab. 54(1): 335-337 (2014) - [j43]Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi:
Efficient implementation of error correction codes in hash tables. Microelectron. Reliab. 54(1): 338-340 (2014) - [j42]Mustafa Demirci, Pedro Reviriego, Juan Antonio Maestro:
Optimized parallel decoding of difference set codes for high speed memories. Microelectron. Reliab. 54(11): 2645-2648 (2014) - [j41]Pedro Reviriego, Salvatore Pontarelli, Alfonso Sánchez-Macián, Juan Antonio Maestro:
A Method to Extend Orthogonal Latin Square Codes. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1635-1639 (2014) - 2013
- [j40]Burak Karsli, Pedro Reviriego, M. Fatih Balli, Oguz Ergin, Juan Antonio Maestro:
Enhanced Duplication: a Technique to Correct Soft Errors in Narrow Values. IEEE Comput. Archit. Lett. 12(1): 13-16 (2013) - [j39]Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro:
Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction. IEEE Des. Test 30(2): 87-95 (2013) - [j38]Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong:
Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication. Microprocess. Microsystems 37(8-D): 1103-1107 (2013) - [j37]Salvatore Pontarelli, Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro:
Low Complexity Concurrent Error Detection for Complex Multiplication. IEEE Trans. Computers 62(9): 1899-1903 (2013) - [j36]Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi:
A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 479-483 (2013) - [j35]Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro, Marco Ottavi:
Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories. IEEE Trans. Circuits Syst. II Express Briefs 60-II(7): 432-436 (2013) - [j34]Zhen Gao, Pedro Reviriego, Wen Pan, Zhan Xu, Ming Zhao, Jing Wang, Juan Antonio Maestro:
Efficient Arithmetic-Residue-Based SEU-Tolerant FIR Filter Design. IEEE Trans. Circuits Syst. II Express Briefs 60-II(8): 497-501 (2013) - [j33]Pedro Reviriego, Oscar Ruano, Mark F. Flanagan, Salvatore Pontarelli, Juan Antonio Maestro:
An Efficient Technique to Protect Serial Shift Registers Against Soft Errors. IEEE Trans. Circuits Syst. II Express Briefs 60-II(8): 512-516 (2013) - [j32]Costas Argyrides, Pedro Reviriego, Juan Antonio Maestro:
Using Single Error Correction Codes to Protect Against Isolated Defects and Soft Errors. IEEE Trans. Reliab. 62(1): 238-243 (2013) - [j31]Pedro Reviriego, Juan Antonio Maestro, Mark F. Flanagan:
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 156-159 (2013) - [j30]Pedro Reviriego, Salvatore Pontarelli, Juan Antonio Maestro:
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2334-2338 (2013) - [c13]Pedro Reviriego, Shih-Fu Liu, Juan Antonio Maestro, S. Lee, Nur A. Touba, Rudrajit Datta:
Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes. DFTS 2013: 167-171 - 2012
- [j29]Pedro Reviriego, Juan Antonio Maestro, José Alberto Hernández, David Larrabeiti:
Study of the potential energy savings in Ethernet by combining Energy Efficient Ethernet and Adaptive Link Rate. Trans. Emerg. Telecommun. Technol. 23(3): 227-233 (2012) - [j28]Pedro Reviriego, Costas Argyrides, Juan Antonio Maestro:
Efficient error detection in Double Error Correction BCH codes for memory applications. Microelectron. Reliab. 52(7): 1528-1530 (2012) - [j27]Pedro Reviriego, Oscar Ruano, Juan Antonio Maestro:
Implementing Concurrent Error Detection in Infinite-Impulse-Response Filters. IEEE Trans. Circuits Syst. II Express Briefs 59-II(9): 583-586 (2012) - [j26]Pedro Reviriego, Mark F. Flanagan, Shih-Fu Liu, Juan Antonio Maestro:
Multiple Cell Upset Correction in Memories Using Difference Set Codes. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(11): 2592-2599 (2012) - [j25]José Luis García-Dorado, Eduardo Magaña, Pedro Reviriego, Mikel Izal, Daniel Morató, Juan Antonio Maestro, Javier Aracil, Jorge E. López de Vergara:
Network monitoring for energy efficiency in large-scale networks: the case of the Spanish Academic Network. J. Supercomput. 62(3): 1284-1304 (2012) - [j24]Shih-Fu Liu, Pedro Reviriego, Juan Antonio Maestro:
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 148-156 (2012) - [c12]Pedro Reviriego, Vijay Sivaraman, Zhi Zhao, Juan Antonio Maestro, Arun Vishwanath, Alfonso Sánchez-Macián, Craig Russell:
An energy consumption model for Energy Efficient Ethernet switches. HPCS 2012: 98-104 - [c11]Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro:
Low Power embedded DRAM caches using BCH code partitioning. IOLTS 2012: 79-83 - 2011
- [j23]Juan Antonio Maestro, Pedro Reviriego, Costas Argyrides, Dhiraj K. Pradhan:
Fault Tolerant Single Error Correction Encoders. J. Electron. Test. 27(2): 215-218 (2011) - [j22]Pedro Reviriego, Ken Christensen, Juan Rabanillo, Juan Antonio Maestro:
An Initial Evaluation of Energy Efficient Ethernet. IEEE Commun. Lett. 15(5): 578-580 (2011) - [j21]Pedro Reviriego, Juan Antonio Maestro, Chris J. Bleakley:
Implications of energy efficient Ethernet for hubs and switches. Int. J. Commun. Networks Distributed Syst. 6(1): 3-11 (2011) - [j20]Pedro Reviriego, Lars Holst, Juan Antonio Maestro:
On the expected longest length probe sequence for hashing with separate chaining. J. Discrete Algorithms 9(3): 307-312 (2011) - [j19]Pedro Reviriego, Shanshan Liu, Juan Antonio Maestro:
Mitigation of permanent faults in adaptive equalizers. Microelectron. Reliab. 51(3): 703-710 (2011) - [j18]Chris J. Bleakley, Pedro Reviriego, Juan Antonio Maestro:
Low-complexity Concurrent Error Detection for convolution with Fast Fourier Transforms. Microelectron. Reliab. 51(6): 1152-1156 (2011) - [j17]Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego:
A fast and efficient technique to apply Selective TMR through optimization. Microelectron. Reliab. 51(12): 2388-2401 (2011) - [j16]David Larrabeiti, Pedro Reviriego, José Alberto Hernández, Juan Antonio Maestro, Manuel Urueña:
Towards an energy efficient 10 Gb/s optical ethernet: Performance analysis and viability. Opt. Switch. Netw. 8(3): 131-138 (2011) - [j15]Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro, Anne O'Donnell:
Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution. IEEE Trans. Computers 60(10): 1511-1516 (2011) - [j14]Pedro Reviriego, Chris J. Bleakley, Juan Antonio Maestro:
Structural DMR: A Technique for Implementation of Soft-Error-Tolerant FIR Filters. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 512-516 (2011) - [j13]Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong:
Mitigating the effects of large multiple cell upsets (MCUs) in memories. ACM Trans. Design Autom. Electr. Syst. 16(4): 45:1-45:10 (2011) - [c10]Pedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg:
Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors. DAC 2011: 700-705 - [c9]Oscar Ruano, Juan Antonio Maestro, Pedro Reviriego:
Validation and optimization of TMR protections for circuits in radiation environments. DDECS 2011: 399-400 - [c8]Pedro Reviriego, Ken Christensen, Alfonso Sánchez-Macián, Juan Antonio Maestro:
Using Coordinated Transmission with Energy Efficient Ethernet. Networking (1) 2011: 160-171 - [c7]Pedro Reviriego, Alfonso Sánchez-Macián, Juan Antonio Maestro:
On the Impact of the TCP Acknowledgement Frequency on Energy Efficient Ethernet Performance. Networking Workshops 2011: 265-272 - 2010
- [j12]Ken Christensen, Pedro Reviriego, Bruce Nordman, Michael Bennett, Mehrgan Mostowfi, Juan Antonio Maestro:
IEEE 802.3az: the road to energy efficient ethernet. IEEE Commun. Mag. 48(11): 50-56 (2010) - [j11]Pedro Reviriego, José Alberto Hernández, David Larrabeiti, Juan Antonio Maestro:
Burst Transmission for Energy-Efficient Ethernet. IEEE Internet Comput. 14(4): 50-57 (2010) - [j10]Pedro Reviriego, Juan Antonio Maestro, Shih-Fu Liu:
Efficient Soft Error-Tolerant Adaptive Equalizers. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 2032-2040 (2010) - [j9]Juan Antonio Maestro, Pedro Reviriego:
Energy Efficiency in Industrial Ethernet: The Case of Powerlink. IEEE Trans. Ind. Electron. 57(8): 2896-2903 (2010) - [j8]Pedro Reviriego, Juan Antonio Maestro, Chris J. Bleakley:
Reliability analysis of memories protected with BICS and a per-word parity bit. ACM Trans. Design Autom. Electr. Syst. 15(2): 18:1-18:15 (2010)
2000 – 2009
- 2009
- [j7]Pedro Reviriego, José Alberto Hernández, David Larrabeiti, Juan Antonio Maestro:
Performance evaluation of energy efficient ethernet. IEEE Commun. Lett. 13(9): 697-699 (2009) - [j6]Juan Antonio Maestro, Pedro Reviriego, Pilar Reyes, Oscar Ruano:
Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study. Integr. 42(2): 128-136 (2009) - [j5]Juan Antonio Maestro, Pedro Reviriego:
A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets. Microelectron. Reliab. 49(7): 707-715 (2009) - [j4]Pedro Reviriego, Juan Antonio Maestro:
Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS. ACM Trans. Design Autom. Electr. Syst. 14(1): 18:1-18:10 (2009) - [j3]Juan Antonio Maestro, Pedro Reviriego:
Reliability of Single-Error Correction Protected Memories. IEEE Trans. Reliab. 58(1): 193-201 (2009) - [c6]Pedro Reviriego, Juan Antonio Maestro, Anne O'Donnell, Chris J. Bleakley:
Soft error detection and correction for FFT based convolution using different block lengths. IOLTS 2009: 138-143 - 2008
- [j2]Pilar Reyes, Pedro Reviriego, Juan Antonio Maestro, Oscar Ruano:
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study. J. Signal Process. Syst. 52(3): 231-247 (2008) - [c5]Juan Antonio Maestro, Pedro Reviriego:
Study of the effects of MBUs on the reliability of a 150 nm SRAM device. DAC 2008: 930-935 - 2007
- [c4]Oscar Ruano, Pilar Reyes, Juan Antonio Maestro, Luca Sterpone, Pedro Reviriego:
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques. DDECS 2007: 261-266 - 2004
- [j1]Juan Antonio Maestro, Daniel Mozos, Raquel Dormido, Pedro Reviriego:
New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study. Des. Autom. Embed. Syst. 9(3): 193-210 (2004)
1990 – 1999
- 1999
- [c3]Juan Antonio Maestro, Daniel Mozos, Román Hermida:
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach. DATE 1999: 766-767 - 1998
- [c2]Juan Antonio Maestro, Daniel Mozos, Hortensia Mecha:
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. DATE 1998: 218-225 - [c1]Juan Antonio Maestro, Daniel Mozos, Julio Septién:
A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Proces. EUROMICRO 1998: 10309-10312
Coauthor Index
[j89] [c17] [j85] [j84] [j83] [j82] [j81] [j80] [j79] [j78] [j77] [j76] [j75] [j74] [j73] [j72] [j71] [j70] [j69] [j68] [j67] [j66] [j65] [j64] [j63] [j62] [j61] [j60] [j59] [j58] [j57] [j56] [j55] [c15] [j54] [j53] [j52] [j51] [j50] [j49] [c14] [j48] [j47] [j46] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [j37] [j36] [j35] [j34] [j33] [j32] [j31] [j30] [c13] [j29] [j28] [j27] [j26] [j25] [j24] [c12] [c11] [j23] [j22] [j21] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [j13] [c10] [c9] [c8] [c7] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [c6] [j2] [c5] [c4] [j1]
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