default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDHLDVT 2003: San Francisco, CA, USA
- Eighth IEEE International High-Level Design Validation and Test Workshop 2003, San Francisco, CA, USA, November 12-14, 2003. IEEE Computer Society 2003, ISBN 0-7803-8236-6
Invited Special Session
- Sandeep K. Shukla, Ramesh Karri
, Seth Copen Goldstein, Forrest Brewer, Kaustav Banerjee, Sankar Basu:
Nano, quantum, and molecular computing: are we ready for the validation and test challenges? 3-7
Processor Validation and Test
- Xiaoliang Bai, Li Chen, Sujit Dey:
Software-based self-test methodology for crosstalk faults in processors. 11-16 - Merav Aharoni, Sigal Asaf, Laurent Fournier, Anatoly Koyfman, Raviv Nagel:
FPgen - a test generation framework for datapath floating-point verification. 17-22 - Allon Adir, Eyal Bin, Ofer Peled, Avi Ziv:
Piparazzi: a test program generator for micro-architecture flow verification. 23-28
High-Level Design Transformations
- K. C. Shashidhar, Maurice Bruynooghe, Francky Catthoor, Gerda Janssens:
Automatic functional verification of memory oriented global source code transformations. 31-36 - Flávio Miana de Paula, Claudionor José Nunes Coelho Jr., Harry Foster, José Augusto Miranda Nacif, Joseph Tompkins, Antônio Otávio Fernandes, Diógenes Cecilio da Silva Jr.:
Refactoring digital hardware designs with assertion libraries. 37-42 - Jennifer Campbell, Nancy A. Day:
High-level optimization of pipeline design. 43-48
SAT and Applications
- Sivaram Gopalakrishnan, Vijay Durairaj, Priyank Kalla:
Integrating CNF and BDD based SAT solvers. 51-56 - Dhiraj K. Pradhan:
Logic transformation and coding theory-based frameworks for Boolean satisfiability. 57-62 - Rajat Arora, Michael S. Hsiao:
Enhancing SAT-based equivalence checking with static logic implications. 63-68
System-Level Issues
- Fulvio Corno, Paolo Gabrielli, Simonluca Tosato:
Relating vehicle-level and network-level reliability through high-level fault injection. 71-76 - Patrick Schaumont, Kazuo Sakiyama, Yi Fan, David D. Hwang, Shenglin Yang, Alireza Hodjat, Bo-Cheng Lai, Ingrid Verbauwhede:
Testing ThumbPod: Softcore bugs are hard to find. 77-82 - Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe:
Verifying LOC based functional and performance constraints. 83-88
Functional Vector Generation and Coverage
- Markus Braun, Wolfgang Rosenstiel, Klaus-Dieter Schubert:
Comparison of Bayesian networks and data mining for coverage directed verification category simulation-based verification. 91-95 - Shai Fine, Avi Ziv:
Enhancing the control and efficiency of the covering process [logic verification]. 96-101 - Íñigo Ugarte, Pablo Sanchez:
Functional vector generation for assertion-based verification at behavioral level using interval analysis. 102-107 - Franco Fummi, Cristina Marconcini, Graziano Pravadelli:
Redundant functional faults reduction by saboteurs synthesis [logic verification]. 108-113
Advances in Sequential Verification
- Kameshwar Chandrasekar, Michael S. Hsiao:
ATPG-based preimage computation: efficient search space pruning with ZBDD. 117-122 - Daniel Große, Rolf Drechsler:
BDD-based verification of scalable designs. 123-128 - Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jérôme Rampon:
Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking. 129-134 - Dhiraj K. Pradhan, Serkan Askar, Maciej J. Ciesielski:
Mathematical framework for representing discrete functions as word-level polynomials. 135-139
Behavioral/System-Level Test Case Generation
- Olga Goloubeva, Matteo Sonza Reorda, Massimo Violante:
High-level test generation for hardware testing and software validation. 143-148 - Roy Emek, Yehuda Naveh:
Scheduling of transactions for system-level test-case generation. 149-154
Comparisons and Evaluations
- Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Li-C. Wang:
A comparison of BDDs, BMC, and sequential SAT for model checking. 157-162 - Alessandro Fin, Franco Fummi:
Genetic algorithms: the philosopher's stone or an effective solution for high-level TPG? 163-168 - Emilio Gaudette, Michael Moussa, Ian G. Harris:
A method for the evaluation of behavioral fault models. 169-172
Panel
- Moshe Levinger, Avi Ziv, Brian Bailey, Jacob Abraham, Bob Bentley, William H. Joyner, Yaron Kas:
Panel: What's the next 'big thing' in simulation-based verification? 175
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-18 01:23 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
