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2020 – today
- 2022
[j5]Harry Foster, Rob Oshana, Jörg Henkel, Vivek De:
Report on the Design Automation Conference (DAC 2021). IEEE Des. Test 39(1): 97-99 (2022)- 2021
- [c20]Harry Foster:
General Chair's Message. DAC 2021: 1
2010 – 2019
- 2018
- [c19]Harry Foster:
2018 FPGA Functional Verification Trends. MTV 2018: 40-45 - 2015
- [c18]Harry D. Foster:
Trends in functional verification: a 2014 industry study. DAC 2015: 48:1-48:6 - 2013
- [c17]Harry Foster:
Why the design productivity gap never happened. ICCAD 2013: 581-584 - [c16]Harry Foster:
Keynote talk III: Industry pulse: Trends in function verification. MEMOCODE 2013: 129-130 - 2010
- [j4]Onur Guzey, Li-C. Wang
, Jeremy R. Levitt, Harry Foster:
Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(1): 138-148 (2010) - [c15]Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor:
Bridging pre-silicon verification and post-silicon validation. DAC 2010: 94-95
2000 – 2009
- 2009
- [j3]Harry Foster:
Applied Assertion-Based Verification: An Industry Perspective. Found. Trends Electron. Des. Autom. 3(1): 1-95 (2009) - [c14]Harry Foster:
Pain, Possibilities, and Prescriptions Industry Trends in Advanced Functional Verification. Haifa Verification Conference 2009: 2 - 2008
- [c13]Harry Foster:
Assertion-Based Verification: Industry Myths to Realities (Invited Tutorial). CAV 2008: 5-10 - [c12]Onur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster:
Functional test selection based on unsupervised support vector analysis. DAC 2008: 262-267 - 2007
- [c11]Sunil Kakkar, Janick Bergeron, Brian Bailey, Harry Foster, Ian Harris:
Panel: Unified approach leading to a seamlessly evolving test bench for all phases of a multi-core design, validation and production test. HLDVT 2007: 167-168 - 2006
- [c10]Janick Bergeron, Harry Foster, Andrew Piziali, Raj Shekher Mitra, Catherine Ahlschlager, Doron Stein:
Building a verification test plan: trading brute force for finesse. DAC 2006: 805-806 - [c9]Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley:
Panel: Assertion-Based Verification -What's the Big Deal? HLDVT 2006: 183 - 2005
- [c8]Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso:
Is methodology the highway out of verification hell? DAC 2005: 521-522 - [c7]Rich Faris, Ken Larsen, Harry Foster, Stuart Swan:
Are Today's Verification Tools Able to Handle Current Design Challenges? ICCD 2005: 77 - 2004
- [b2]Harry Foster, Adam Krolnik, David Lacey:
Assertion-based design, Second Edition. Kluwer 2004, ISBN 978-1-4020-8027-2, pp. I-XXIII, 1-390 - [c6]Harry Foster:
Panel: Driving the intelligent testbanch: are we there yet? HLDVT 2004: 188 - [c5]Fernando Cortez Sica, Claudionor José Nunes Coelho Jr., José Augusto Miranda Nacif, Harry Foster, Antônio Otávio Fernandes:
Exception handling in microprocessors using assertion libraries. SBCCI 2004: 55-59 - 2003
- [c4]Flávio Miana de Paula, Claudionor José Nunes Coelho Jr., Harry Foster, José Augusto Miranda Nacif, Joseph Tompkins, Antônio Otávio Fernandes, Diógenes Cecilio da Silva Jr.:
Refactoring digital hardware designs with assertion libraries. HLDVT 2003: 37-42 - [c3]José Augusto Miranda Nacif, Claudionor Nunes Coelho, Harry Foster, Flávio Miana de Paula, Edjard Mota, Márcia Roberta Falcão Mota, Antônio Otávio Fernandes:
On-Chip Property Verification Using Assertion Processors. VLSI-SoC (Selected Papers) 2003: 101-117 - [c2]José Augusto Miranda Nacif, Flávio Miana de Paula, Harry Foster, Claudionor José Nunes Coelho Jr., Antônio Otávio Fernandes:
The Chip is Ready. Am I done? On-chip Verification using Assertion Processors. VLSI-SOC 2003: 111- - 2002
- [c1]David L. Dill, Nate James, Shishpal Rawat, Gérard Berry, Limor Fix, Harry Foster, Rajeev K. Ranjan, Gunnar Stålmarck, Curt Widdoes:
Formal verification methods: getting around the brick wall. DAC 2002: 576-577 - 2001
- [b1]Lionel Bening, Harry Foster:
Principles of verifiable RTL design - a functional coding style supporting verification processes in Verilog. Kluwer 2001, ISBN 978-0-7923-7368-1, pp. I-XXIII, 1-281 - [j2]Harry Foster:
Applied Boolean Equivalence Verification and RTL Static Sign-Off. IEEE Des. Test Comput. 18(4): 6-15 (2001) - [j1]Lionel Bening, Harry Foster:
Optimizing Multiple EDA Tools within the ASIC Design Flow. IEEE Des. Test Comput. 18(4): 46-55 (2001)
Coauthor Index
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